假设有两个VHDL模块,COMPONENT EDK_modulePORT(CLK_P:在std_logic中; CLK_N:在std_logic中; ------ ------); END COMPONENT; COMPONENT ISE_modulePORT(CLK_P:在std_logic中; CLK_N:在std_logic中)
; ------ ------); END COMPONENT;如果ML605板有跟随网clk_in_p LOC = J9 | IOSTANDARD = LVDS_25 | DIFF_TERM = TRUE; NET clk_in_n LOC = H9 | IOSTANDARD = LVDS_25 | DIFF_TERM =
TRUE;差异clk,1)如何将上述时钟映射到两个组件(EDK_module和ISE_module)?(它不能直接映射,因为它们将共享相同的clk缓冲区)2)关于回复注释,如何制作
通过OBUFDS差异clk?
以上来自于谷歌翻译
以下为原文
Assume, there are two VHDL modules,
COMPONENT EDK_module
PORT (
CLK_P : in std_logic;
CLK_N : in std_logic;
------
------
);
END COMPONENT;
COMPONENT ISE_module
PORT (
CLK_P : in std_logic;
CLK_N : in std_logic;
------
------
);
END COMPONENT;
If the ML605 board has a following
NET clk_in_p LOC = J9 |IOSTANDARD = LVDS_25 |DIFF_TERM = TRUE;
NET clk_in_n LOC = H9 |IOSTANDARD = LVDS_25 |DIFF_TERM = TRUE;
differential clk,
1) How can I map the above clock to both components (EDK_module and ISE_module)?
(It can't be mapped directly as they will share the same clk buffer)
2) Regarding the reply comment, how to make a differential clk through OBUFDS?
假设有两个VHDL模块,COMPONENT EDK_modulePORT(CLK_P:在std_logic中; CLK_N:在std_logic中; ------ ------); END COMPONENT; COMPONENT ISE_modulePORT(CLK_P:在std_logic中; CLK_N:在std_logic中)
; ------ ------); END COMPONENT;如果ML605板有跟随网clk_in_p LOC = J9 | IOSTANDARD = LVDS_25 | DIFF_TERM = TRUE; NET clk_in_n LOC = H9 | IOSTANDARD = LVDS_25 | DIFF_TERM =
TRUE;差异clk,1)如何将上述时钟映射到两个组件(EDK_module和ISE_module)?(它不能直接映射,因为它们将共享相同的clk缓冲区)2)关于回复注释,如何制作
通过OBUFDS差异clk?
以上来自于谷歌翻译
以下为原文
Assume, there are two VHDL modules,
COMPONENT EDK_module
PORT (
CLK_P : in std_logic;
CLK_N : in std_logic;
------
------
);
END COMPONENT;
COMPONENT ISE_module
PORT (
CLK_P : in std_logic;
CLK_N : in std_logic;
------
------
);
END COMPONENT;
If the ML605 board has a following
NET clk_in_p LOC = J9 |IOSTANDARD = LVDS_25 |DIFF_TERM = TRUE;
NET clk_in_n LOC = H9 |IOSTANDARD = LVDS_25 |DIFF_TERM = TRUE;
differential clk,
1) How can I map the above clock to both components (EDK_module and ISE_module)?
(It can't be mapped directly as they will share the same clk buffer)
2) Regarding the reply comment, how to make a differential clk through OBUFDS?
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