我希望我理解你的问题，但我的第一印象是你已经在UCF文件中分配了一些带有你设计I / O端口的引脚。
但是在您的设计中，您已经删除了I / O缓冲区，因此这些端口不再连接到任何逻辑。
可能会发生合成工具移除未连接的信号。
我希望您澄清有关您的UCF PIN分配和设计I / O端口的更多信息。
以上来自于谷歌翻译
以下为原文
I hope I understand your question right, but my first impression would be that you have assigned some pins in UCF files with I/O ports of your design. But in your design you have removed the I/O buffers so these ports are not connected any more to any logic. It can happen that the synthesis tool remove unconnected signals.
I wish if you clarify more about your UCF PIN assignment and your design I/O ports.
我希望我理解你的问题，但我的第一印象是你已经在UCF文件中分配了一些带有你设计I / O端口的引脚。
但是在您的设计中，您已经删除了I / O缓冲区，因此这些端口不再连接到任何逻辑。
可能会发生合成工具移除未连接的信号。
我希望您澄清有关您的UCF PIN分配和设计I / O端口的更多信息。
以上来自于谷歌翻译
以下为原文
I hope I understand your question right, but my first impression would be that you have assigned some pins in UCF files with I/O ports of your design. But in your design you have removed the I/O buffers so these ports are not connected any more to any logic. It can happen that the synthesis tool remove unconnected signals.
I wish if you clarify more about your UCF PIN assignment and your design I/O ports.
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