为什么在路由设计过程中出现此警告消息

嗨，
我在设计中使用了部件xc7a200tifbv676-1L（Artix7）。
我正在使用Vivado 2017.1。在“路线设计”阶段我得到了警告.....完成了无矢量传播活动传播警告：[Designutils 20-266]家庭artix7的电压源VCCINTIO无效。
忽略电压设置。警告：[Designutils 20-266]家庭artix7的电压源VCCINTIO无效。
忽略电压设置。警告：[Designutils 20-266]家庭artix7的电压源VCCINTIO无效。
忽略电压设置。警告：[Designutils 20-266]家庭artix7的电压源VCCINTIO无效。
忽略电压设置。警告：[Designutils 20-266]家庭artix7的电压源VCCINTIO无效。
忽略电压设置。警告：[Designutils 20-266]家庭artix7的电压源VCCINTIO无效。
忽略电压设置...在日志消息窗口中，它显示为：[Designutils 20-266]家庭artix7的无效电压源VCCINTIO。
忽略电压设置。
以下约束（以及其他）在我的xdc文件中，但我不明白哪个可以负责.set_property INTERNAL_VREF 0.750 [get_iobanks 12] set_property INTERNAL_VREF 0.750 [get_iobanks 14] set_property IOSTANDARD LVCMOS33 [get_ports {slot *} set_property IOSTandard
LVCMOS15 [get_ports {a7_rsvd *}] set_property IOSTANDARD LVCMOS33 [get_ports {a7_phy_ *}] set_property IOSTANDARD LVCMOS15 [get_ports {sf2_a7_ *}] set_property CONFIG_VOLTAGE 1.5 [current_design] set_property CFGBVS GND [current_design]
任何人都可以对此有所了解吗？
谢谢。
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以下为原文

Hi,

I am using the part xc7a200tifbv676-1L (Artix7) in a design. I am using Vivado 2017.1.

During 'Route-Design' stage I get the warning...
.
.
Finished Running Vector-less Activity Propagation
WARNING: [Designutils 20-266] Invalid Voltage Source VCCINTIO for the family artix7. Ignoring the voltage setting.
WARNING: [Designutils 20-266] Invalid Voltage Source VCCINTIO for the family artix7. Ignoring the voltage setting.
WARNING: [Designutils 20-266] Invalid Voltage Source VCCINTIO for the family artix7. Ignoring the voltage setting.
WARNING: [Designutils 20-266] Invalid Voltage Source VCCINTIO for the family artix7. Ignoring the voltage setting.
WARNING: [Designutils 20-266] Invalid Voltage Source VCCINTIO for the family artix7. Ignoring the voltage setting.
WARNING: [Designutils 20-266] Invalid Voltage Source VCCINTIO for the family artix7. Ignoring the voltage setting.
.
.

In the log Messages window it is displayed as:
[Designutils 20-266] Invalid Voltage Source VCCINTIO for the family artix7. Ignoring the voltage setting.

These following constraints (among others) are in my xdc file, but I don't understand which one can be responsible.

set_property INTERNAL_VREF  0.750    [get_iobanks 12]
set_property INTERNAL_VREF  0.750    [get_iobanks 14]
set_property IOSTANDARD LVCMOS33  [ get_ports {slot*}        
set_property IOSTANDARD LVCMOS15  [ get_ports {a7_rsvd*   }]
set_property IOSTANDARD LVCMOS33  [ get_ports {a7_phy_* } ]
set_property IOSTANDARD LVCMOS15  [ get_ports {sf2_a7_*  } ]

set_property CONFIG_VOLTAGE  1.5   [current_design]
set_property CFGBVS                  GND   [current_design]


Can anyone throw some light on this?

Thanks.
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FPGA enthusiast!
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