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[问答]

Virtex6怎么配置寄存器初始值

你好
我想配置寄存器初始值。
有任何约束(UCF)可以实现吗?
环境
-  Virtex6
-  ISE 14.7

以上来自于谷歌翻译


以下为原文

Hello


I want to configure register initial value.
Have any constraint(UCF) can implement?

Environment
-- Virtex6
-- ISE 14.7

回帖(4)

李铃华

2018-10-26 15:10:05
FPGA使用默认初始值,在启动后立即执行progaramme。
对于任何特定值,您可以使用内存初始化。
对于注册,您可以直接在代码中定义。
您也可以使用data2mem实用程序
谢谢和RegardsBalkrishan -----------------------------------------------
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FPGA use default initial value which will progaramme immediately after power on . For any specific value you can use memory initialization.

For register you can define directly in your code.  

You can also use data2mem utility as well



Thanks and Regards
Balkrishan
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廖阿朋

2018-10-26 15:24:18
你好@ balkris
我想配置DFF初始值。

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Hello @balkris
 
I want to configure DFF initial value.
 
 
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李铃华

2018-10-26 15:41:25
您只需初始化HDL代码即可。
谢谢和RegardsBalkrishan -----------------------------------------------
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You can just initialize in your HDL code .Thanks and Regards
Balkrishan
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Please mark the post as an answer "Accept as solution" in case it helped resolve your query.
Give kudos in case a post in case it guided to the solution.
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吕钢格

2018-10-26 15:49:02
嗨@ quincyq2003,
你能分享用于初始化FF的代码吗?
因为FF的值会随着时钟边沿而改变,如果你使用的是高频时钟,那么你可能无法注意到它。
谢谢,Arpan -----------------------------------------------
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如果提供的信息有用,请将答案标记为“接受为解决方案”。给予您认为有用且回复的帖子。感谢Kudos .--------------------
--------------------------------------------------
------------------------

以上来自于谷歌翻译


以下为原文

Hi @quincyq2003,
 
Can you share the code used to initialize FF?
Because the value of FF will change with the clock edge and if you are using high frequency clock then you may not be able to notice the same.
Thanks,
Arpan
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