如何定位超级逻辑区域

@bdillahuntdra，
为什么要确保设计中的新代码放在其他SLR中？
这将不必要地增加导致时序违规的延迟。
请查看UG下面的第73页：
http://www.xilinx.com/support/documentation/sw_manuals/ug949-vivado-design-methodology.pdf
问候，
赛义德
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以下为原文

@bdillahuntdra,
 
Why would you want to make sure that the new code in the design get placed in other SLR? 
This would unnecessarily add delays leading to timing violations.
 
Please check out page number 73 in below UG:
http://www.xilinx.com/support/documentation/sw_manuals/ug949-vivado-design-methodology.pdf
 
Regards,
Syed
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b，
这些工具会自动将您的设计划分为SLR。
这对你来说应该不用担心。
时序约束自然会导致智能分区，并且不需要锁定任何放置。
在设计完成后（逻辑），IO应该被分配，以便不会以使得最终设计不太理想的方式约束放置。
查看Steve Leibson最近关于OOC的博客，并使用之前的捕获来加速实施微小变化。
Austin Lesea主要工程师Xilinx San Jose



以下为原文

b,
 
The tools will automatically partition your design among the SLR's.  This should be of no concern to you.  Timing constraints naturally lead to intelligent partitions, and there should be no need to lock down any placement.  IO should get assigned after the design is done (the logic) so as to not constrain the placement in ways that will make the resulting design less optimal.
 
Look at Steve Leibson's recent blogs on OOC and using prior captures to speed up implementing small changes.
 
 
 
 
Austin Lesea
Principal Engineer
Xilinx San Jose

在某些情况下，您可能需要手动分配到SLR。如果工具找不到满足设计要求的解决方案，或者运行间重复性很重要，则可能需要手动SLR分配。
要执行手动SLR分配：
1.创建大型PBlock（区域组）。
2.将设计的部分分配给这些区域组。
要将设计的大部分分配给单个SLR：
1.创建包含单个SLR的PBlock。
2.将逻辑的关联层次结构分配给该PBlock。
虽然您可以为多个相邻的SLR组件分配逻辑，但您必须确保PBlock包含整个SLR。
希望这可以帮助。
问候
Sikta



以下为原文

In certain conditions, you might need manual assignment to SLR. Manual SLR assignment might be necessary when the tools do not find a solution that meets design requirements, or when run-to-run repeatability is important.
To perform manual SLR assignment:
1. Create large PBlocks (area groups).
2. Assign portions of the design to those area groups.
 
To assign large sections of the design to a single SLR:
1. Create a PBlock that encompasses a single SLR.
2. Assign the associated hierarchy of the logic to that PBlock.
 
While you can assign logic to multiple adjacent SLR components, you must ensure that the PBlock encompasses the entire SLR.
 
Hope this helps.
 
Regards
Sikta

@bdillahuntdra，
上述共享信息是否已回答您的问题？
--Syed
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以下为原文

@bdillahuntdra,
 
Did the above shared information answered your query?
 
--Syed
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