dsPIC33EP32MC502 PWM无法启动

我使用代码配置器在这个PIC上设置PWM，但是似乎不能得到输出。我用MICROStiCK2作为我的基础。下面是我的振荡器和PWM初始化的代码。我看了很难，但找不到任何错误的代码。有什么想法，为什么不工作？谢谢



      以下为原文

    I am using Code Configurator  to set up PWM on this PIC but can't seem to get an output. I am using Microstick2 as my base. Below is the code for my Oscillator and PWM initialization. I have looked hard but cannot find anything wrong in the code. Any thoughts why this isn't working?
Thanks

void OSCILLATOR_Initialize(void)
{
    // CF no clock failure; NOSC FRCPLL; CLKLOCK unlocked; OSWEN Switch is Complete;
    __builtin_write_OSCCONL((uint8_t) (0x100 & 0x00FF));
    // FRCDIV FRC/1; PLLPRE 2; DOZE 1:8; PLLPOST 1:2; DOZEN disabled; ROI disabled;
    CLKDIV = 0x3000;
    // TUN Center frequency;
    OSCTUN = 0x0;
    // ROON disabled; ROSEL disabled; RODIV Base clock value; ROSSLP disabled;
    REFOCON = 0x0;
    // PLLDIV 64;
    PLLFBD = 0x40;
    // RND disabled; SATB disabled; SATA disabled; ACCSAT disabled;
CORCONbits.RND = 0;
CORCONbits.SATB = 0;
CORCONbits.SATA = 0;
CORCONbits.ACCSAT = 0;
}

void PWM_Initialize (void)
{
    // PCLKDIV 1;
    PTCON2 = 0x0;
    // PTPER 1023;
    PTPER = 0x3FF;
    // SEVTCMP 0;
    SEVTCMP = 0x0;
    // MDC 0;
    MDC = 0x0;
    // CHOPCLK 0; CHPCLKEN disabled;
    CHOP = 0x0;
    // PWMKEY 0;
    PWMKEY = 0x0;
    // MDCS Primary; FLTIEN disabled; CAM Edge Aligned; DTC Dead-time function is disabled; TRGIEN disabled; XPRES disabled; ITB Master; IUE disabled; CLIEN disabled; MTBS disabled; DTCP disabled;
    PWMCON1 = 0x80;
    // MDCS Primary; FLTIEN disabled; CAM Edge Aligned; DTC Positive dead time; TRGIEN disabled; XPRES disabled; ITB Master; IUE disabled; CLIEN disabled; MTBS disabled; DTCP disabled;
    PWMCON2 = 0x0;
    // MDCS Primary; FLTIEN disabled; CAM Edge Aligned; DTC Positive dead time; TRGIEN disabled; XPRES disabled; ITB Master; IUE disabled; CLIEN disabled; MTBS disabled; DTCP disabled;
    PWMCON3 = 0x0;
    //FLTDAT PWM1L Low, PWM1H Low; SWAP disabled; OVRENH disabled; PENL enabled; PMOD Redundant Output Mode; OVRENL disabled; OSYNC disabled; POLL disabled; PENH enabled; CLDAT PWM1L Low, PWM1H Low; OVRDAT PWM1L Low, PWM1H Low; POLH disabled;
    __builtin_write_PWMSFR(&IOCON1, 0xC400, &PWMKEY);
    //FLTDAT PWM2L Low, PWM2H Low; SWAP disabled; OVRENH disabled; PENL disabled; PMOD Complementary Output Mode; OVRENL disabled; OSYNC disabled; POLL disabled; PENH disabled; CLDAT PWM2L Low, PWM2H Low; OVRDAT PWM2L Low, PWM2H Low; POLH disabled;
    __builtin_write_PWMSFR(&IOCON2, 0x0, &PWMKEY);
    //FLTDAT PWM3L Low, PWM3H Low; SWAP disabled; OVRENH disabled; PENL disabled; PMOD Complementary Output Mode; OVRENL disabled; OSYNC disabled; POLL disabled; PENH disabled; CLDAT PWM3L Low, PWM3H Low; OVRDAT PWM3L Low, PWM3H Low; POLH disabled;
    __builtin_write_PWMSFR(&IOCON3, 0x0, &PWMKEY);
    //FLTPOL disabled; CLPOL disabled; CLSRC FLT1; CLMOD disabled; FLTMOD Fault input is disabled; FLTSRC FLT32;
    __builtin_write_PWMSFR(&FCLCON1, 0xFB, &PWMKEY);
    //FLTPOL disabled; CLPOL disabled; CLSRC FLT1; CLMOD disabled; FLTMOD PWM2H, PWM2L pins to FLTDAT values- Latched; FLTSRC FLT32;
    __builtin_write_PWMSFR(&FCLCON2, 0xF8, &PWMKEY);
    //FLTPOL disabled; CLPOL disabled; CLSRC FLT1; CLMOD disabled; FLTMOD PWM3H, PWM3L pins to FLTDAT values- Latched; FLTSRC FLT32;
    __builtin_write_PWMSFR(&FCLCON3, 0xF8, &PWMKEY);
    // PDC1 511;
    PDC1 = 0x1FF;
    // PDC2 0;
    PDC2 = 0x0;
    // PDC3 0;
    PDC3 = 0x0;
    // PHASE1 0;
    PHASE1 = 0x0;
    // PHASE2 0;
    PHASE2 = 0x0;
    // PHASE3 0;
    PHASE3 = 0x0;
    // DTR1 0;
    DTR1 = 0x0;
    // DTR2 0;
    DTR2 = 0x0;
    // DTR3 0;
    DTR3 = 0x0;
    // ALTDTR1 0;
    ALTDTR1 = 0x0;
    // ALTDTR2 0;
    ALTDTR2 = 0x0;
    // ALTDTR3 0;
    ALTDTR3 = 0x0;
    // TRGCMP 0;
    TRIG1 = 0x0;
    // TRGCMP 0;
    TRIG2 = 0x0;
    // TRGCMP 0;
    TRIG3 = 0x0;
    // TRGDIV 1; TRGSTRT 0;
    TRGCON1 = 0x0;
    // TRGDIV 1; TRGSTRT 0;
    TRGCON2 = 0x0;
    // TRGDIV 1; TRGSTRT 0;
    TRGCON3 = 0x0;
    // BPLL disabled; BPHH disabled; BPLH disabled; BCH disabled; FLTLEBEN disabled; PLR disabled; CLLEBEN disabled; BCL disabled; PLF disabled; PHR disabled; BPHL disabled; PHF disabled;
    LEBCON1 = 0x0;
    // BPLL disabled; BPHH disabled; BPLH disabled; BCH disabled; FLTLEBEN disabled; PLR disabled; CLLEBEN disabled; BCL disabled; PLF disabled; PHR disabled; BPHL disabled; PHF disabled;
    LEBCON2 = 0x0;
    // BPLL disabled; BPHH disabled; BPLH disabled; BCH disabled; FLTLEBEN disabled; PLR disabled; CLLEBEN disabled; BCL disabled; PLF disabled; PHR disabled; BPHL disabled; PHF disabled;
    LEBCON3 = 0x0;
    // LEB 0;
    LEBDLY1 = 0x0;
    // LEB 0;
    LEBDLY2 = 0x0;
    // LEB 0;
    LEBDLY3 = 0x0;
    // CHOPLEN disabled; CHOPHEN disabled; BLANKSEL No state blanking; CHOPSEL No state blanking;
    AUXCON1 = 0x0;
    // CHOPLEN disabled; CHOPHEN disabled; BLANKSEL No state blanking; CHOPSEL No state blanking;
    AUXCON2 = 0x0;
    // CHOPLEN disabled; CHOPHEN disabled; BLANKSEL No state blanking; CHOPSEL No state blanking;
    AUXCON3 = 0x0;
   

    // SYNCOEN disabled; SEIEN disabled; SESTAT disabled; SEVTPS 1; SYNCSRC SYNCI1; SYNCEN disabled; PTSIDL disabled; PTEN enabled; EIPU disabled; SYNCPOL disabled;
    PTCON = 0x8000;
}