dsPIC33EP32GS502奇怪的PWM行为

您好。我在我的DSIC33 EP32 GS502（包SO28）板上遇到了一些问题。在将代码上传到设备（使用PICtiT3）之后，我可以在示波器上看到PWM，无论是PWM1H还是PWM1L（互补的，中心对齐模式）。但是在断开PICTIT3之后，PWM板消失了，只有PWM、核心工作良好（LED闪烁、UART保持发送/接收等）。由于程序员连接器只使用GoalPin阵列，当决定改变设备的频率源时，这个PWM问题开始发生，只需要对UART通信有更大的稳定性，因此增加16MHz石英（制造新的PCB）。检查频率请求和获得：FPLLI＝16MHZ／lt；PLLPRE 2＋2和gt；＝48MHZ频率要求为0.8MHZFVCO＝4MHZ＊& lt；PLLDIV 58＋2和gt；＝240MHZ频率要求为120 MHz & lt；fvCo和lt；340MHZOFCC＝240MHZ／lt；2 * PLLPOST & Gt；＝120 MHZ频率要求为lt＝120 MHZI。认为一切都很好，UART和计时器运行，所以必须罚款？由于需要60MHz的指令周期，不能使用FVCO作为PWM用途（MAX是120 MHz，而我有240MHz），所以必须使用FRC作为APLL的辅助振荡器时钟源。FPLL＝7.37 MHz×16＝11792MHz，满足小于1MHz和大于112MHz的要求。所以它应该很好，还是我错过了什么？也用示波器和X100探头（我没有任何FET探头）检查晶体振荡器得到预期的正弦信号（16MHz）。振荡电容器为C0G介质型22PF@ 50V情况0402，加1M电阻跨振荡器。测量电压：VCAP＝1.96V（电容器为10uf@ 20V陶瓷，外壳0805，X7R），VDD＝3.44 V。两种电压均为平滑、无尖峰等。VDD上升时间＝2.2MS（0～3.44 V），因此应满足POR定时器（PoR定时器）。最小1V/ms根据数据表）。不幸的是，有简单的线性调节器KA33 RM（78线），所以它可能比开关调节器的阶跃响应更差，但仍然应该工作（在加电后和之后没有发现任何电压下降）。在DSPIC和CAPS之间的跟踪比最大推荐长度短，在DSPIC和CAPS之间的跟踪之前，CAPS是最早的。不知道如何进行PWM工作。希望有人能帮助我解决这个问题。下面附上一些源代码。配置（来自MCC）振荡器功能（来自MCC）：PWM初始化功能



      以下为原文

    Hello.
I got some problems with PWM on my dsPIC33EP32GS502 (package SO28) board.
After upload code to device (using PICkit3) I can see PWM on oscilloscope, both PWM1H and PWM1L (complementary, center-aligned mode as desired). But after disconnecting PICkit3 form board PWM is gone, only PWM, core is working well (LEDs blinking, UART keep send/recive, etc.). As programmer connector use simply goldpin array.
This PWM problem starts to happen when decided to change frequency source for device, just needed more stability for UART communication, so added 16MHz quartz (made new PCB). Checked frequency requiments and get:

Fplli = 16MHz/ = 4MHz
frequency requiment is 0.8MHz < Fplli < 8.0MHz
Fvco = 4MHz * = 240MHz
frequency requiment is 120MHz < Fvco < 340MHz
Fosc = 240MHz / <2*PLLPOST> = 120MHz
frequency requiment is <= 120MHz

I think everything is fine up there, UART and timers are operating so it have to be fine?

Because needed 60MHz instruction cycle, cannot use Fvco for PWM purpose (max is 120MHz, and I have 240MHz there),  so have to use FRC as auxiliary oscillator clock source for APLL. Fapll = 7.37MHz * 16 = 117.92MHz, it meets requiments less than 120MHz and more than 112MHz. So it should work fine or I miss something?

Checked also crystal oscillator with oscilloscope and x100 probe (I dont have any FET probe) get sinusiodal signal as expected (16MHz). Oscillator capacitors are C0G dielectric type 22pF@50V case 0402, plus 1M resistor across oscillator.
Measured voltages: Vcap = 1.96V (capacitor is 10uF@20V ceramic, case 0805, X7R), Vdd = 3.44V. Both voltages are smooth, no spikes etc.
Vdd rise time = 2.2ms (0-3.44V) so it should satisfy POR timer (min 1V/ms according to datasheet). Unfortunlly theres simply linear regulator KA33RM (78 line) so it probably get worse step response than switching regulator but still should work (never find any voltage drops while and after powerup).
Also put decopuling capacitors as mentioned in data sheet (Chapter2.0 Guidelines...  RECOMMENDED MINIMUM CONNECTION) - caps are first before dsPIC in power chain also traces between dsPIC and caps are  shorter than maximum recommended length.

Have no idea how to made PWM work.
Hope someone of You guys can help me with this issue.
Below attached some source code.

Configuration (from MCC):
// FOSCSEL
#pragma config FNOSC = PRIPLL    // Oscillator Source Selection->Primary Oscillator with PLL module (XT + PLL, HS + PLL, EC + PLL)
#pragma config IESO = ON    // Two-speed Oscillator Start-up Enable bit->Start up device with FRC, then switch to user-selected oscillator source

// FOSC
#pragma config POSCMD = HS    // Primary Oscillator Mode Select bits->HS Crystal Oscillator Mode
#pragma config OSCIOFNC = OFF    // OSC2 Pin Function bit->OSC2 is clock output
#pragma config IOL1WAY = ON    // Peripheral pin select configuration bit->Allow only one reconfiguration
#pragma config FCKSM = CSECME    // Clock Switching Mode bits->Both Clock switching and Fail-safe Clock Monitor are enabled
#pragma config PLLKEN = ON    // PLL Lock Enable Bit->Clock switch to PLL source will wait until the PLL lock signal is valid

Oscillator function (from MCC):
void OSCILLATOR_Initialize(void)
{
    // CF no clock failure; NOSC PRIPLL; CLKLOCK unlocked; OSWEN Switch is Complete;
    __builtin_write_OSCCONL((uint8_t) (0x300 & 0x00FF));
    // FRCDIV FRC/1; PLLPRE 4; DOZE 1:1; PLLPOST 1:2; DOZEN disabled; ROI disabled;
    CLKDIV = 0x2;
    // TUN Center frequency;
    OSCTUN = 0x0;
    // ROON disabled; ROSEL disabled; RODIV Base clock value; ROSSLP disabled;
    REFOCON = 0x0;
    // PLLDIV 58;
    PLLFBD = 0x3A;
    // ENAPLL enabled; APSTSCLR 1:1; FRCSEL FRC; SELACLK Auxiliary Oscillators; ASRCSEL No clock input;
    ACLKCON = 0xA740;
    // LFSR 0;
    LFSR = 0x0;
}

PWM Initialize function


#define DEF_MIN_F 12625

#define PWM_DT_100ns 96



void Initialize_PWM(void)
{
    IOCON1bits.PENH = 1; // PWM1H controlled by PWM module
    IOCON1bits.PENL = 1; // PWM1L controlled by PWM module
    IOCON1bits.PMOD = 0; // PWML & PWMH complementary

    IOCON2bits.PENH = 0;
    IOCON2bits.PENL = 0;

    PWMCON1bits.CAM = 1; // Set Center-aligned mode
    PWMCON1bits.ITB = 1; // Independent Timebase requied for Center-aligned mode
    PWMCON1bits.DTC = 0; // Positive Dead Time

    PHASE1 = DEF_MIN_F; // set starting freq
    PHASE1 = (PHASE1 & 0b1111111111111000);

    PDC1 = DEF_MIN_F/2; // set duty cycle

    ALTDTR1 = (PWM_DT_100ns); // set dead time
}