分频时钟馈送DCM错误

我将源时钟除以2，然后尝试将其输入DCM（首先通过缓冲区）。
但我得到的错误是我无法解释的：
错误：NgdBuild：455  - 逻辑网络'clk25'有多个驱动程序：块clk25上的引脚Q，类型为FDC，块上的引脚PAD为clk25.PAD，类型为PADERROR：NgdBuild：462  - 输入焊盘网'clk25'驱动多个
缓冲器：块cgate / u_ibuf上的引脚I，类型为IBUF，引脚I上的块clk25_INV_1_o1_INV_0，类型为INVERROR：NgdBuild：924  - 输入焊盘网'clk25'驱动非缓冲原语：块c上的引脚Q，类型为FDC
我还在.bld文件中找到了一些INFO消息，我不明白。
信息：NgdBuild：889  - 在此设计中，Pad net'clk25'未连接到外部端口。
添加了一个新端口'clk25'并连接到该信号。
我只是将时钟分成如下，然后将clk25送入DCM：
cg1：进程（clk_src，rst）如果rst ='1'则开始，然后clk25 elsif clk_src'event和clk_src ='1'然后clk25结束if;
结束过程;



以下为原文

I am dividing my source clock by 2, then trying to feed this into a DCM (through a buffer first). But I get errors which I cannot explain:

ERROR:NgdBuild:455 - logical net 'clk25' has multiple driver(s):
     pin Q on block clk25 with type FDC,
     pin PAD on block clk25.PAD with type PAD
ERROR:NgdBuild:462 - input pad net 'clk25' drives multiple buffers:
     pin I on block cgate/u_ibuf with type IBUF,
     pin I on block clk25_INV_1_o1_INV_0 with type INV
ERROR:NgdBuild:924 - input pad net 'clk25' is driving non-buffer primitives:
     pin Q on block clk25 with type FDC


I also found some INFO message in the .bld file, which I don't understand.

INFO:NgdBuild:889 - Pad net 'clk25' is not connected to an external port in this
design.  A new port 'clk25' has been added and is connected to this signal.

I am simply dividing the clock as below, then feeding clk25 into the DCM:

  cg1 : process(clk_src, rst)
  begin
    if rst = '1' then
      clk25 <= '0';
    elsif clk_src'event and clk_src='1' then
      clk25 <= not clk25;
    end if;
  end process;