如何在xilinx中制作RPM？

您需要阅读约束指南的RLOC部分：
http://www.xilinx.com/support/documentation/sw_manuals/xilinx11/cgd.pdf
本应用笔记涵盖了其他一些没有详细记录的问题。
我十年前使用Virtex-II示例编写了它，但所有RPM信息仍然相关：
http://www.xilinx.com/support/documentation/application_notes/xapp416.pdf
基于切片的RPM存在一个问题，即它们需要与原点一起放置在正确的切片类型中以维持预期的相对切片位置。
如果设置了变量XIL_PAR_ALIGN_USER_RPMS并且宏围绕切片切片的最左下方切片构建，则自动放置将仅正确处理此问题。
有关宏来源的更多信息，请参阅上面的appnote。
使用FPGA编辑器检查生成的宏。
列表窗口可以设置为“用户定义的宏”，然后您可以从列表中选择它们以使它们变暗。



以下为原文

You'll want to read the RLOC section of the constraints guide:
http://www.xilinx.com/support/documentation/sw_manuals/xilinx11/cgd.pdf
 
This appnote covers some other issues that aren't well documented. I wrote it ten years ago using a Virtex-II example, but all of the RPM information is still relevant:
http://www.xilinx.com/support/documentation/application_notes/xapp416.pdf
 
There is a problem with slice based RPMs in that they need to be placed with the origin in the correct slice type to maintain the intended relative slice positions. Automatic placement will only handle this correctly if the variable XIL_PAR_ALIGN_USER_RPMS is set and the macro is constructed around the lower left most slice of a slice tile. See the above appnote for more information about macro origins.
 
Use FPGA Editor to examine the resulting macros. The list window can be set to "User Defined Macros" and then you can select them from the list to hilight them.
 
 

嗨bwade，
我遵循指南，我设法将RLOC约束放在verilog中用于单比特FF。
例如：
（* RLOC_GRID =“GRID”*）//在模块实例化之前声明一次。
（* RLOC =“X3Y4”*）
reg sample_reg;
同样也放在其他FF上。
问题是我无法在总线上放置RLOC约束。
喜欢
reg [3：0] sample_bus;
XST只是忽略它并根据需要映射组件。
你能告诉我我可能做错了什么，或者如何在公交车上放置RLOC约束？
谢谢



以下为原文

Hi bwade,
I followed the guide and well I managed to place RLOC constraints in verilog for single bit FFs. for example:
 
 
(* RLOC_GRID =  "GRID" *) // declaring once before module instantiation.
(* RLOC = "X3Y4" *)
reg sample_reg;
 
and similarly placing on other FFs as well.
 
The problem is that I can't place RLOC constraints on buses. like
reg [3:0] sample_bus;
 
XST simply ignores it and maps the components as it likes.
 
Can you kindly tell me what i might be doing wrong or how can I place RLOC constraints on buses ?
 
Thanks
 
 

此外，当我以相同的方式将约束放置到BRAM实例时，忽略它说层次结构中没有RLOC参数。我忘了提及，我的目标设备是spartan3 xc3s4000。



以下为原文

Also, when i place the constraints in the same manner to BRAM instance, it is ignored saying that there's no parameter with RLOC in the hierarchy.
And I forgot to mention, my targeted device is spartan3 xc3s4000.

这应该是“RPM_GRID”而不是“RLOC_GRID”，但这不会对宏创建产生影响，它只会改变坐标的解释方式。
我不确定为什么你的RLOC约束没有传递给FF实例，因为这更像是一个综合问题而不是实现问题。
您始终可以使用UCF约束来更正它。
请记住，RLOC必须位于相同的层次结构块中才能创建默认集。
如果不是，则还需要应用U_SET约束。
如果宏仅包含切片逻辑，则无需使用RPM网格。
请参阅前面引用的appnote，以讨论该主题。



以下为原文

That should be "RPM_GRID" not "RLOC_GRID" but that wouldn't make a difference in the macro creation, it only changes how the coordinates are interpreted. I'm not sure why your RLOC constraints aren't getting passed to the FF instances as that's more of a synthesis issue than an implementation issue. You can always use UCF constraints to correct that. Keep in mind that the RLOCs have to be in the same hierarchy block for the default set to be created. If they're not, you need to also apply U_SET constraints. You don't need to use RPM grid if the macro only contains slice logic. See the appnote I referenced earlier for a discussion of that topic.