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如何在一个四核中使用两个gtx收发器用于两个极光ips

赫拉mgt银行是113
我正在使用两个极光ips 64b66b。对于一个ip GTX_X1Y0,另一个GTX_X1Y2。在模拟时,结果很好。在MAP中实现它的实现中的显示错误。
包装:2811  - 定向包装无法遵守用户设计约束(LOC = GTXE2_COMMON_X1Y1),这要求将下面列出的符号组合打包到单个GTXE2_COMMON组件中。定向包不可能,因为:目标组件类型可以
涉及的符号包括:GTXE2_COMMON符号“Source2 / Aurora_2 / src_2_wrapper_i / Src_2_multi_gt_i / gtxe2_common_i”(输出信号= NULL)GTXE2_COMMON符号“Source1 / Aurora_1 / src_1_wrapper_i / Src_1_multi_gt_i / gtxe2_common_i”(输出信号= NULL)
它的解决方案是什么?
找到附件。

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hera mgt bank is 113
i am using two aurora ips 64b66b .for one ip GTX_X1Y0, another GTX_X1Y2.while simulating ,results are good.Coming to implementation its showing error in implementaion.that in MAP.

Pack:2811 - Directed packing was unable to obey the user design constraints (LOC=GTXE2_COMMON_X1Y1) which requires the combination of the symbols listed below to be packed into a single GTXE2_COMMON component.
The directed pack was not possible because: The target component type can only contain one fragment.
The symbols involved are:
GTXE2_COMMON symbol "Source2/Aurora_2/src_2_wrapper_i/Src_2_multi_gt_i/gtxe2_common_i" (Output Signal = NULL)
GTXE2_COMMON symbol "Source1/Aurora_1/src_1_wrapper_i/Src_1_multi_gt_i/gtxe2_common_i" (Output Signal = NULL)

What is the solution for it?

find attachments.

回帖(9)

姚庭芳

2018-9-28 11:28:33
你好@ rajuponnaganti
看起来你试图在一个四核中使用两个GTXE2_COMMON块。
您必须使用一个GTXE2_COMMON块,因为您在一个块中使用两个GTX。
谢谢,
维奈
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Hi @rajuponnaganti
 
It looks like you are trying to use two GTXE2_COMMON blocks in one quad.
You have to use one GTXE2_COMMON block since you are using two GTXs from one block.
 
Thanks,
Vinay
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王山崎

2018-9-28 11:46:21
您应该将一个Aurora核心的共享逻辑配置为包含在核心中,并将第二个Aurora核心的共享逻辑配置在示例设计中。技术上,核心中具有共享逻辑的核心称为主,另一个称为从核

Master包含公共实例,并向slave提供gtrefclkout。请参阅http://www.xilinx.com/support/documentation/ip_documentation/aurora_64b66b/v10_0/pg074-aurora-64b66b.pdf的“共享逻辑”部分。
有关框图,请参见相同PG的图3-17,其中显示了主站和从站之间的互连。
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You should configure one Aurora core's shared logic to be included within the core and the second Aurora  core's shared logic to be included in the example design.

Technically, the core with shared logic in the core is called as master and the other is called as slave. Master contains common instantiation in it and provides the gtrefclkout to the slave.

Please refer to "Shared Logic" section of http://www.xilinx.com/support/documentation/ip_documentation/aurora_64b66b/v10_0/pg074-aurora-64b66b.pdf

Refer to Figure 3-17 of the same PG for block diagram showing the inter-connectivity between master and slave.-----------------------------------------------------------------------------------------------
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王山崎

2018-9-28 11:54:22
我看到了你的重复帖子-http://forums.xilinx.com/t5/Implementation/QPLL-loc-constraints/mp/640380#M13011http://forums.xilinx.com/t5/General-Technical-Discussion/problem
-in-using-two-GTX-Transceivers-X1Y0-and-X1Y1 / mp / 640350#M34780请避免重复发帖。
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I saw duplicate posts from you-
http://forums.xilinx.com/t5/Implementation/QPLL-loc-constraints/m-p/640380#M13011
http://forums.xilinx.com/t5/General-Technical-Discussion/problem-in-using-two-GTX-Transceivers-X1Y0-and-X1Y1/m-p/640350#M34780

Please avoid duplicate posts.-----------------------------------------------------------------------------------------------
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Give Kudos to a post which you think is helpful.
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许海明

2018-9-28 12:12:14
我不是在使用vivado。
我正在使用ise 14.7,设备xc7vx485tboard vc707

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i am not using vivado. i am using ise 14.7, device xc7vx485t
board vc707
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