DDR布线参考

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DDR布线参考

Hardware and Layout Design Considerations for DDR Memory Interfaces

Embedded systems that utilize double data rate memory
(DDR) can realize increased performance over traditional
single data rate (SDR) memories. As the name implies, DDR
enables two data transactions to occur within a single clock
cycle without having to double the applied clock or without
having to double the size of the data bus. This increased data
bus performance is achieved by the introduction of
source-synchronous data strobes that permit data to be
captured on both the falling and rising edges of the strobe.
Although DDR can bring improved performance to an
embedded design, care must be observed in the schematic
and layout phases to ensure that desired performance is
realized. Smaller setup and hold times, cleaner reference
voltages, tighter trace matching, new I/O (SSTL-2)
signaling, and the need for proper termination can present
the board designer with a new set of challenges that were not
present for SDR designs.

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