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# add wave * # view structure # .main_pane.structure.interior.cs.body.struct # view signals # .main_pane.objects.interior.cs.body.tree # run -all # ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). # Time: 0 ps Iteration: 0 Instance: /svpwm_1_vhd_tst/i1/b2v_inst9 # ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0. # Time: 0 ps Iteration: 0 Instance: /svpwm_1_vhd_tst/i1/b2v_inst9 # ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). # Time: 0 ps Iteration: 0 Instance: /svpwm_1_vhd_tst/i1/b2v_inst9 # ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0. # Time: 0 ps Iteration: 0 Instance: /svpwm_1_vhd_tst/i1/b2v_inst9 # ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). # Time: 0 ps Iteration: 0 Instance: /svpwm_1_vhd_tst/i1/b2v_inst9 # ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0. # Time: 0 ps Iteration: 0 Instance: /svpwm_1_vhd_tst/i1/b2v_inst9 # ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). # Time: 0 ps Iteration: 0 Instance: /svpwm_1_vhd_tst/i1/b2v_inst8 # ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0. # Time: 0 ps Iteration: 0 Instance: /svpwm_1_vhd_tst/i1/b2v_inst8 # ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). # Time: 0 ps Iteration: 0 Instance: /svpwm_1_vhd_tst/i1/b2v_inst8 # ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0. # Time: 0 ps Iteration: 0 Instance: /svpwm_1_vhd_tst/i1/b2v_inst8 # ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). # Time: 0 ps Iteration: 0 Instance: /svpwm_1_vhd_tst/i1/b2v_inst8 # ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0. # Time: 0 ps Iteration: 0 Instance: /svpwm_1_vhd_tst/i1/b2v_inst8 我已经赋过初值了,测试激励也写入了,但会跳出这些,下面是我第八第九模块VHDL源程序。 求教,网上找了很多,也改了好多次,都不行。 这里两个模块的输入主要是三相正弦电压用八位二进制表示来输入,我怀疑应该是出错在我把Uab,Ubc,Uca从std_logic_vector转换成INTEGER时,语句不对或者格式不对。 求大神指点! ================第八模块:矢量作用时间================== library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity vector_time is Port(Ts: in INTEGER; Ud: in INTEGER; Uab: in std_logic_vector(7 downto 0); Ubc: in std_logic_vector(7 downto 0); Uca: in std_logic_vector(7 downto 0); N:in INTEGER; Tx: out INTEGER; Ty: out INTEGER); end vector_time; architecture Behavioral of vector_time is signal x, y : INTEGER:=0; signal ab,bc,ca: INTEGER range 0 to 255; begin ab <= conv_integer(Uab); bc <= conv_integer(Ubc); ca <= conv_integer(Uca); process(ab,bc,ca,N) begin case N is when 1=>x<=bc;y<=ab; when 2=>x<=-ab;y<=-ca; when 3=>x<=ca;y<=bc; when 4=>x<=-bc;y<=-ab; when 5=>x<=ab;y<=ca; when 6=>x<=-ca;y<=-bc; when others=>null; end case; end process; Tx <= x*Ts/Ud; Ty <= y*Ts/Ud; end Behavioral; ==================第九模块:扇区判别=================== library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity sector is Port(Uab:in std_logic_vector(7 downto 0); Ubc:in std_logic_vector(7 downto 0); Uca:in std_logic_vector(7 downto 0); N:out INTEGER ); end sector; architecture Behavioral of sector is signal x:STD_LOGIC_VECTOR(2 downto 0); signal ab,bc,ca:INTEGER range 0 to 255; begin ab <= conv_integer(Uab); bc <= conv_integer(Ubc); ca <= conv_integer(Uca); x(2)<='1' when ab >= 0 else'0'; x(1)<='1' when bc >= 0 else'0'; x(0)<='1' when ca >= 0 else'0'; process(x) begin case x is when"110"=>N<=1; when"010"=>N<=2; when"011"=>N<=3; when"001"=>N<=4; when"101"=>N<=5; when"100"=>N<=6; when others=>null; end case; end process; end Behavioral; |
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