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library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity zdshj is port(clk:in std_logic; set,buy,sel,finish:in std_logic; coin1,coin5:in std_logic; money1,money5:out std_logic; price,quantity:in std_logic_vector(3 downto 0); display,act:out std_logic_vector(3 downto 0); y0,y1:out std_logic_vector(6 downto 0)); end zdshj; architecture behav of zdshj #type ram_type is array(3 downto 0)of std_logic_vector(7 downto 0) #signal ram:ram_type; signal clk1:std_logic; signal item:std_logic_vector(1 downto 0); signal cnt:std_logic_vector(3 downto 0); signal pri,qua:std_logic_vector(3 downto 0); begin P0:process(set,clk1) variable quan:std_logic_vector(3 downto 0); begin if set='1' then ram(conv_integer(item))<=price & quantity; act<="0000"; elsif clk1'event and clk1='1' then money1<='0'; money5<='0'; if coin1='1' then if cnt<"1001" then cnt<=cnt+1; else cnt<="0000"; end if; elsif coin5='1' then if cnt<"1001" then cnt<=cnt+5; else cnt<="0000"; end if; elsif sel='1' then item<=item+1; elsif get='1' then if qua>"0000" and cnt>=pri then cnt<=cnt-pri; quan:=quan-1; ram(conv_integer(item))<=pri & quan; if item="00" then act<="1000"; elsif item="01" then act<="0100"; elsif item="10" then act<="0010"; elsif item="11" then act<="0001"; end if; end if; elsif finish='1' then if cnt>"0101" then money5<='1'; cnt<=cnt-5; elsif cnt>"0000" then money1<='1'; cnt<=cnt-1; else money5<='0'; money1<='0'; end if; elsif get='0' then act<="0000"; for i in 4 to 7 loop pri(i-4)<=ram(conv_integer(item))(i); end loop; for i in 0 to 3 loop quan(i)=:ram(conv_integer(item))(i); end loop; end if; end if; qua<=quan; end process P0; m50:process(clk) variable Q:std_logic_vector(24 downto 0); begin if clk'event and clk='1' then Q=:Q+1; end if; if Q="1011111010111100000111111" then clk1<='1'; else clk1<='0'; end if; end process m50; code0:process(item) begin case item is when "00"=> display0<="0111"; when "01"=> display0<="1011"; when "10"=> display0<="1101"; when others=> display0<="1110"; end case; end process code0; code1:process(cnt) begin case cnt is when "0000"=>y0<="0000001"; when "0001"=>y0<="1001111"; when "0010"=>y0<="0010010"; when "0011"=>y0<="0000110"; when "0100"=>y0<="1001100"; when "0101"=>y0<="0100100"; when "0110"=>y0<="0100000"; when "0111"=>y0<="0001111"; when "1000"=>y0<="0000000"; when "1001"=>y0<="0000100"; when others=>y0<="1111111"; end case; end process code1; code2:process(qua) begin case when "0000"=>y1<="0000001"; when "0001"=>y1<="1001111"; when "0010"=>y1<="0010010"; when "0011"=>y1<="0000110"; when "0100"=>y1<="1001100"; when "0101"=>y1<="0100100"; when "0110"=>y1<="0100000"; when "0111"=>y1<="0001111"; when "1000"=>y1<="0000000"; when "1001"=>y1<="0000100"; when others=>y1<="1111111"; end case; end process code2; end behav; |
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1个回答
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就是有#号的两句,编译提示是Error (10500): VHDL syntax error at zdshj.vhd(15) near text "type"; expecting "is"
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