二进制码转BCD码

module bit_bcd(clk,rst,data_in,data_out);

module bit_bcd(clk,rst,data_in,data_out);
input clk,rst;
input[7:0] data_in;
output[11:0] data_out;
reg[3:0]cnt;
reg [3:0] state;
reg [19:0]data_reg;

parameter start = 4'b0001,
      yiwei = 4'b0010,
      panduan = 4'b0100,
      idle = 4'b1000;
always@(posedge clk or negedge rst)
if(!rst) begin
cnt<=4'd0;
state<=start;
end
else
case(state)
start:begin cnt<=4'd0;
data_reg<={12'd0,data_in};
state<=yiwei;

end
yiwei:begin
   state<=panduan;
data_reg<=(data_reg<<1);
cnt<=cnt+1'b1;
end
panduan:
   if(cnt==4'd8)
   state<=idle;
   else
      if(data_reg[11:8]>=3'b101) begin
      data_reg<=data_reg+10'b1100000000;
   state<=yiwei;
   end
      else if(data_reg[15:12]>=3'b101) begin
      data_reg<=data_reg+14'b11000000000000;
   state<=yiwei;
   end
   else
   state<=yiwei;
idle:begin cnt<=4'd0;
   state<=idle;
   if (data_reg[11:8]>=4'd10) begin
   data_reg[11:8]<=data_reg[11:8]-4'd10;
   data_reg[15:12]<=data_reg[15:12]+1'b1;
   end
   else if(data_reg[15:12]>=4'd10) begin
   data_reg[15:12]<=data_reg[15:12]-4'd10;
   data_reg[19:16]<=data_reg[19:16]+1'b1;
   end
   end
default:state<=start;
endcase

assign  data_out = data_reg[19:8];



endmodule