完善资料让更多小伙伴认识你,还能领取20积分哦, 立即完善>
扫一扫,分享给好友
串口接收完数据利用数码管显示出来,并将接收到的数据发回给pc,每次只发送或接收一帧数据,显示最多用两个数码管,可是数码管只显示00,且无法将接收到的数据发送回去,程序挺简单,有人能帮忙看看程序的错误么??
以下是接收模块 module usart_rx ( clk,rst_n,clk_bps,start_rx,rs232_in,bps_start,rx_data,rx_finish ); input clk; input clk_bps; input rst_n; input start_rx; input rs232_in; output bps_start; output[7:0]rx_data; output rx_finish; reg[3:0]count; reg bps_start_r; reg rx_finish; reg[7:0]rx_data_r; always@(posedge clk or negedge rst_n) if(!rst_n) begin count<=4'd0; bps_start_r<=1'b0; rx_finish<=1'b0; rx_data_r<=8'd0; end else case(count) 4'd0:if(start_rx)begin bps_start_r<=1'b1;count<=count+1'b1;end 4'd1:if(clk_bps)begin count<=count+1'b1;end 4'd2:if(clk_bps)begin rx_data_r[0]<=rs232_in;count<=count+1'b1;end 4'd3:if(clk_bps)begin rx_data_r[1]<=rs232_in;count<=count+1'b1;end 4'd4:if(clk_bps)begin rx_data_r[2]<=rs232_in;count<=count+1'b1;end 4'd5:if(clk_bps)begin rx_data_r[3]<=rs232_in;count<=count+1'b1;end 4'd6:if(clk_bps)begin rx_data_r[4]<=rs232_in;count<=count+1'b1;end 4'd7:if(clk_bps)begin rx_data_r[5]<=rs232_in;count<=count+1'b1;end 4'd8:if(clk_bps)begin rx_data_r[6]<=rs232_in;count<=count+1'b1;end 4'd9:if(clk_bps)begin rx_data_r[7]<=rs232_in;count<=count+1'b1;end 4'd10:if(clk_bps)count<=count+1'b1; 4'd11:if(clk_bps)count<=count+1'b1; 4'd12:begin bps_start_r<=1'b0;count<=count+1'b1;end 4'd13:begin rx_finish<=1'b1;count<=1'd0;end default:; endcase assign bps_start=bps_start_r; assign rx_data=rx_data_r; endmodule 以下是发送模块 module usart_tx ( clk,rst_n,clk_bps,rx_data,rx_finish,rs232_out,bps_start ); input clk; input rst_n; input rx_finish; input clk_bps; input[7:0] rx_data; output rs232_out; output bps_start; reg[7:0]tx_data; reg[3:0]count1; reg bps_start_r; reg start_tx; reg rs232_out_r; always@(posedge clk or negedge rst_n) if(!rst_n) begin count1<=4'd0; start_tx<=1'b0; bps_start_r<=1'b0; tx_data<=8'd0; end else if(rx_finish) begin start_tx<=1'b1; bps_start_r<=1'b1; tx_data<=rx_data; end else case(count1) 4'd0:if(clk_bps)begin rs232_out_r<=1'b0;count1<=count1+1'b1;end 4'd1:if(clk_bps)begin rs232_out_r<=tx_data[0];count1<=count1+1'b1;end 4'd2:if(clk_bps)begin rs232_out_r<=tx_data[1];count1<=count1+1'b1;end 4'd3:if(clk_bps)begin rs232_out_r<=tx_data[2];count1<=count1+1'b1;end 4'd4:if(clk_bps)begin rs232_out_r<=tx_data[3];count1<=count1+1'b1;end 4'd5:if(clk_bps)begin rs232_out_r<=tx_data[4];count1<=count1+1'b1;end 4'd6:if(clk_bps)begin rs232_out_r<=tx_data[5];count1<=count1+1'b1;end 4'd7:if(clk_bps)begin rs232_out_r<=tx_data[6];count1<=count1+1'b1;end 4'd8:if(clk_bps)begin rs232_out_r<=tx_data[7];count1<=count1+1'b1;end 4'd9:if(clk_bps)begin rs232_out_r<=1'b1;count1<=count1+1'b1;end 4'd10:if(clk_bps)begin rs232_out_r<=1'b1;count1<=count1+1'b1;end 4'd11:begin bps_start_r<=1'b0;count1<=count1+1'b1;end 4'd12:begin start_tx<=1'b0;count1<=1'd0;end default:; endcase assign bps_start=bps_start_r; assign rs232_out=rs232_out_r; endmodule 下面是数码管显示部分 module dispay_rx ( clk,rst_n,rx_finish,rx_data,seg_data,scan_sig ); input clk; input rst_n; input rx_finish; input[7:0]rx_data; output[7:0]seg_data; output[5:0]scan_sig; parameter T1MS = 16'd49999; reg[15:0]cnt1; reg[1:0]i1; reg[3:0]number; reg[1:0]i2; reg[5:0]scan_sig_r; always@(posedge clk or negedge rst_n) if(!rst_n ) cnt1 <= 16'd0; else if(cnt1==T1MS) cnt1<=16'd0; else if(rx_finish) cnt1<=cnt1+1'b1; always@(posedge clk or negedge rst_n) if(!rst_n) begin i1<=1'b0; number<=1'd0; end else if(rx_finish) case(i1) 1'b0:if(cnt1==T1MS)i1<=i1+1'b1;else number<=rx_data[7:4]; 1'b1:if(cnt1==T1MS)i1<=1'b0;else number<=rx_data[3:0]; default:; endcase parameter _0 = 8'b1100_0000, _1 = 8'b1111_1001, _2 = 8'b1010_0100, _3 = 8'b1011_0000, _4 = 8'b1001_1001, _5 = 8'b1001_0010, _6 = 8'b1000_0010, _7 = 8'b1111_1000, _8 = 8'b1000_0000, _9 = 8'b1001_0000, _10= 8'b1000_1000, _11= 8'b1000_0011, _12= 8'b1100_1110, _13= 8'b1010_0001, _14= 8'b1000_0110, _15= 8'b1000_1110; reg[7:0]seg_data_r; always@(posedge clk or negedge rst_n) if(!rst_n) seg_data_r<=8'b11111111; else if(rx_finish) case(number) 4'd0:seg_data_r<=_0; 4'd1:seg_data_r<=_1; 4'd2:seg_data_r<=_2; 4'd3:seg_data_r<=_3; 4'd4:seg_data_r<=_4; 4'd5:seg_data_r<=_5; 4'd6:seg_data_r<=_6; 4'd7:seg_data_r<=_7; 4'd8:seg_data_r<=_8; 4'd9:seg_data_r<=_9; 4'd10:seg_data_r<=_10; 4'd11:seg_data_r<=_11; 4'd12:seg_data_r<=_12; 4'd13:seg_data_r<=_13; 4'd14:seg_data_r<=_14; 4'd15:seg_data_r<=_15; default:; endcase assign seg_data=seg_data_r; always@(posedge clk or negedge rst_n) if(!rst_n) begin i2<=1'b0; scan_sig_r<=6'b100_000; end else if(rx_finish) case(i2) 1'b0:if(cnt1==T1MS)i2<=i2+1'b1;else scan_sig_r<=6'b111_101; 1'b1:if(cnt1==T1MS)i2<=1'b0;else scan_sig_r<=6'b111_110; default:; endcase assign scan_sig=scan_sig_r; endmodule 我用的板子是cyclone4的ep4c |
|
相关推荐
1个回答
|
|
数码管程序没有问题,问题应该主要出在串口接收数据上,大家帮忙看看,我是新手
|
|
|
|
你正在撰写答案
如果你是对答案或其他答案精选点评或询问,请使用“评论”功能。
325 浏览 0 评论
1405 浏览 1 评论
471 浏览 0 评论
求FPGA 驱动控制ltc2271 或者 ltc2180 或者 ltc2190或者 ltc2202 的代码
2094 浏览 0 评论
535 浏览 0 评论
4960 浏览 112 评论
小黑屋| 手机版| Archiver| 电子发烧友 ( 湘ICP备2023018690号 )
GMT+8, 2024-9-12 23:41 , Processed in 0.377934 second(s), Total 43, Slave 35 queries .
Powered by 电子发烧友网
© 2015 bbs.elecfans.com
关注我们的微信
下载发烧友APP
电子发烧友观察
版权所有 © 湖南华秋数字科技有限公司
电子发烧友 (电路图) 湘公网安备 43011202000918 号 电信与信息服务业务经营许可证:合字B2-20210191