大学生在用FPGA做交通灯,尝试多种方法,没有成功

本帖最后由 yuexiangrenshen 于 2015-4-1 14:37 编辑

打开板子后,数码管始终显示0.
下面是代码,请耐心帮忙看一下.
只有红绿黄灯,东西 南北方向的绿灯均显示60秒

Library IEEE ;      
use IEEE.std_logic_1164.all ;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENtiTY CONTROLL IS
PORT(CLK:IN STD_LOGIC;
EN:IN STD_LOGIC;
CON:IN STD_LOGIC;
COUNTNUM:IN INTEGER RANGE 0 TO 120;
A:OUT INTEGER RANGE 0 TO 60;
B:OUT INTEGER RANGE 0 TO 60;
R1,G1,Y1:OUT STD_LOGIC;
R2,G2,Y2:OUT STD_LOGIC);
END CONTROLL;
  ARCHITECTURE behav OF CONTROLL IS
  SIGNAL m:integer range 0 to 3;
  begin
  process(clk,en,con,countnum)
  variable deng:STD_LOGIC_vector(5 downto 0);
  begin
  if (clk'event and clk='1')then
  if en='1'then
   if countnum>60 then
  a<=120-countnum;
  b<=120-countnum;
     if countnum>110 then
  deng:="010100";
     else
   deng:="010100";
   a<=110-countnum;
      end if;
      end if;
  else if countnum>0 then
  b<=60-countnum;
  a<=60-countnum;
    if countnum>50 then
  deng:="001010";
    else
  deng:="100010";
  a<=50-countnum;
    end if;
    end if;
if en='0'then
a<=0;
b<=0;
  if con='1'then
  if m=3 then
  m<=0;
  else
  m<=m+1;
end if;
if m=0 then
   deng:="010100";
elsif m=1 then
  deng:="010100";
elsif m=2 then
  deng:="001010";
elsif m=3 then
  deng:="100010";
end if;
end if;
end if;

r1<=deng(5);
g1<=deng(4);
y1<=deng(3);
r2<=deng(2);
g2<=deng(1);
y2<=deng(0);
end if;
end if;
end process;

end behav;






Library IEEE ;      
use IEEE.std_logic_1164.all ;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity counter is
port
(clk:IN STD_LOGIC;
en:IN STD_LOGIC;
reset:IN STD_LOGIC;
countnum:buffer integer range 0 to 119);
end counter;
  ARCHITECTURE behav OF counter is
begin
  process(reset,clk)
  begin
  if reset='1' then
  countnum<=0;
  elsif CLK'EVENT AND CLK='1' then
  if en='1' then
   if  countnum<119 then
       countnum<=0;
else
countnum<= countnum+1;
end if;
else  countnum<=0;
end if;
end if;
end process;
end behav;




Library IEEE ;      
use IEEE.std_logic_1164.all ;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY fd IS
     PORT(    EN,CLK:IN STD_LOGIC;
               COUT:OUT STD_LOGIC);
END fd;
  ARCHITECTURE behav OF FD IS
  SIGNAL Q:STD_LOGIC;
BEGIN
   PROCESS(CLK,EN)
   VARIABLE TEMP:INTEGER RANGE 2499999 DOWNTO 0:=0;         
   BEGIN
   if EN='1' then
     IF CLK'EVENT AND CLK='1' THEN
      IF TEMP=2499999 THEN
            TEMP:=0;Q<=NOT Q;
       ELSE TEMP:=TEMP+1;
      END IF;
     END IF;
     ELSE
     Q<='0';TEMP:=0;
     END IF;
   END PROCESS;
   COUT<=Q;
END behav;



Library IEEE ;      
use IEEE.std_logic_1164.all ;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY jishu IS
    PORT (EN: IN STD_LOGIC;
            T1,T2: IN INTEGER RANGE 0 TO 60;
          LED1,LED2,LED3,LED4 :OUT STD_LOGIC_VECTOR(3 DOWNTO 0));      
END jishu;
      
      ARCHITECTURE behav OF jishu IS
  SIGNAL L1,L2,L3,L4 : INTEGER RANGE 0 TO 9;
BEGIN

p2:PROCESS(EN,T1,T2)
begin
IF EN='1' THEN
L1<=T1/10;L2<=T1 REM 10;
L3<=T2/10;L4<=T2 REM 10;

END IF;
END PROCESS;
P3:PROCESS(L1)
    BEGIN
      CASE L1 IS
        WHEN 0=>LED1<="0000";
        WHEN 1=>LED1<="0001";
        WHEN 2=>LED1<="0010";
        WHEN 3=>LED1<="0011";
        WHEN 4=>LED1<="0100";
        WHEN 5=>LED1<="0101";
        WHEN 6=>LED1<="0110";
        WHEN 7=>LED1<="0111";
        WHEN 8=>LED1<="1000";
        WHEN 9=>LED1<="1001";
        WHEN OTHERS=> LED1<="0000";
      END CASE;
   END PROCESS;
P4:PROCESS(L2)
    BEGIN
      CASE L2 IS
        WHEN 0=>LED2<="0000";
        WHEN 1=>LED2<="0001";
        WHEN 2=>LED2<="0010";
        WHEN 3=>LED2<="0011";
        WHEN 4=>LED2<="0100";
        WHEN 5=>LED2<="0101";
        WHEN 6=>LED2<="0110";
        WHEN 7=>LED2<="0111";
        WHEN 8=>LED2<="1000";
        WHEN 9=>LED2<="1001";
        WHEN OTHERS=> LED2<="0000";
      END CASE;
   END PROCESS;
P5:PROCESS(L3)
    BEGIN
      CASE L3 IS
         WHEN 0=>LED3<="0000";
        WHEN 1=>LED3<="0001";
        WHEN 2=>LED3<="0010";
        WHEN 3=>LED3<="0011";
        WHEN 4=>LED3<="0100";
        WHEN 5=>LED3<="0101";
        WHEN 6=>LED3<="0110";
        WHEN 7=>LED3<="0111";
        WHEN 8=>LED3<="1000";
        WHEN 9=>LED3<="1001";
        WHEN OTHERS=> LED3<="0000";
      END CASE;
   END PROCESS;
P6:PROCESS(L4)
    BEGIN
      CASE L4 IS
         WHEN 0=>LED4<="0000";
        WHEN 1=>LED4<="0001";
        WHEN 2=>LED4<="0010";
        WHEN 3=>LED4<="0011";
        WHEN 4=>LED4<="0100";
        WHEN 5=>LED4<="0101";
        WHEN 6=>LED4<="0110";
        WHEN 7=>LED4<="0111";
        WHEN 8=>LED4<="1000";
        WHEN 9=>LED4<="1001";
        WHEN OTHERS=> LED4<="0000";
      END CASE;
   END PROCESS;
   END behav;


Library IEEE ;      
use IEEE.std_logic_1164.all ;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY yima IS
     PORT(    EN:IN STD_LOGIC;
              LED1,LED2,LED3,LED4 :IN STD_LOGIC_VECTOR(3 DOWNTO 0);
              LED7S:OUT STD_LOGIC_VECTOR(27 DOWNTO 0):=(OTHERS=>'1'));
END yima;
  ARCHITECTURE behav OF yima IS
SIGNAL REG1:STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL REG2:STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL REG3:STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL REG8:STD_LOGIC_VECTOR(6 DOWNTO 0);
BEGIN
PROCESS(EN,LED1)
BEGIN
IF EN='1'THEN
CASE LED1 IS
WHEN "0000" =>  REG1<="1000000";
WHEN "0001" =>  REG1<="1111001";
WHEN "0010" =>  REG1<="0100100";
WHEN "0011" =>  REG1<="0110000";
WHEN "0100" =>  REG1<="0011001";
WHEN "0101" =>  REG1<="0010010";
WHEN "0110" =>  REG1<="0000010";
WHEN "0111" =>  REG1<="1111000";
WHEN "1000" =>  REG1<="0000000";
WHEN "1001" =>  REG1<="0010000";
WHEN "1010" =>  REG1<="0001000";
WHEN "1011" =>  REG1<="0000011";
WHEN "1100" =>  REG1<="1000110";
WHEN "1101" =>  REG1<="0100001";
WHEN "1110" =>  REG1<="0000110";
WHEN "1111" =>  REG1<="0001110";
WHEN OTHERS=> NULL;
END CASE;
ELSE REG1<="1111111";
END IF;
END PROCESS;

PROCESS(EN,LED2)
BEGIN
IF EN='1'THEN
CASE LED2 IS
WHEN "0000" =>  REG2<="1000000";
WHEN "0001" =>  REG2<="1111001";
WHEN "0010" =>  REG2<="0100100";
WHEN "0011" =>  REG2<="0110000";
WHEN "0100" =>  REG2<="0011001";
WHEN "0101" =>  REG2<="0010010";
WHEN "0110" =>  REG2<="0000010";
WHEN "0111" =>  REG2<="1111000";
WHEN "1000" =>  REG2<="0000000";
WHEN "1001" =>  REG2<="0010000";
WHEN "1010" =>  REG2<="0001000";
WHEN "1011" =>  REG2<="0000011";
WHEN "1100" =>  REG2<="1000110";
WHEN "1101" =>  REG2<="0100001";
WHEN "1110" =>  REG2<="0000110";
WHEN "1111" =>  REG2<="0001110";
WHEN OTHERS=> NULL;
END CASE;
ELSE REG2<="1111111";
END IF;
END PROCESS;
PROCESS(EN,LED3)
BEGIN
IF EN='1'THEN
CASE LED3 IS
WHEN "0000" =>  REG3<="1000000";
WHEN "0001" =>  REG3<="1111001";
WHEN "0010" =>  REG3<="0100100";
WHEN "0011" =>  REG3<="0110000";
WHEN "0100" =>  REG3<="0011001";
WHEN "0101" =>  REG3<="0010010";
WHEN "0110" =>  REG3<="0000010";
WHEN "0111" =>  REG3<="1111000";
WHEN "1000" =>  REG3<="0000000";
WHEN "1001" =>  REG3<="0010000";
WHEN "1010" =>  REG3<="0001000";
WHEN "1011" =>  REG3<="0000011";
WHEN "1100" =>  REG3<="1000110";
WHEN "1101" =>  REG3<="0100001";
WHEN "1110" =>  REG3<="0000110";
WHEN "1111" =>  REG3<="0001110";
WHEN OTHERS=> NULL;
END CASE;
ELSE REG3<="1111111";
END IF;
END PROCESS;

PROCESS(EN,LED4)
BEGIN
IF EN='1'THEN
CASE LED4 IS
WHEN "0000" =>  REG8<="1000000";
WHEN "0001" =>  REG8<="1111001";
WHEN "0010" =>  REG8<="0100100";
WHEN "0011" =>  REG8<="0110000";
WHEN "0100" =>  REG8<="0011001";
WHEN "0101" =>  REG8<="0010010";
WHEN "0110" =>  REG8<="0000010";
WHEN "0111" =>  REG8<="1111000";
WHEN "1000" =>  REG8<="0000000";
WHEN "1001" =>  REG8<="0010000";
WHEN "1010" =>  REG8<="0001000";
WHEN "1011" =>  REG8<="0000011";
WHEN "1100" =>  REG8<="1000110";
WHEN "1101" =>  REG8<="0100001";
WHEN "1110" =>  REG8<="0000110";
WHEN "1111" =>  REG8<="0001110";
WHEN OTHERS=> NULL;
END CASE;
ELSE REG8<="1111111";
END IF;
END PROCESS;

LED7S(27 DOWNTO 21)<=REG1;
LED7S(20 DOWNTO 14)<=REG2;
LED7S(13 DOWNTO 7)<=REG3;
LED7S(6 DOWNTO 0)<=REG8;
END behav;