这段代码是什么意思求大神

1913

问答对人有帮助，内容完整，我也想知道答案 0 component iamge_ana is Port (clk_in : in STD_LOGIC; lock : in std_logic; LOS : in std_logic; COMP : in std_logic; HORI : in std_logic; ODD_EVEN : in std_logic; BACKBORCH : in std_logic; VERT : in std_logic; SYNCAMP : in std_logic; AD_CLK : out std_logic; AD_D : instd_logic_vector(13 downto 0); clk_ana : out std_logic; ena_ana : out std_logic; start_ana : out std_logic; addra_ana : outstd_logic_vector(16 downto 0); dina_ana : outstd_logic_vector(13 downto 0); iamge_ana_state : outstd_logic_vector(7 downto 0); test : out STD_LOGIC_VECTOR (4 downto 0)); end component; entity iamge_ana is Port ( clk_in: in STD_LOGIC; lock : in std_logic; LOS : in std_logic; COMP : in std_logic; HORI : in std_logic; ODD_EVEN : instd_logic; BACKBORCH : instd_logic; VERT : in std_logic; SYNCAMP : instd_logic; AD_CLK : outstd_logic; AD_D : instd_logic_vector(13 downto 0); clk_ana : outstd_logic; ena_ana : outstd_logic; start_ana : outstd_logic; addra_ana : outstd_logic_vector(16 downto 0); dina_ana : outstd_logic_vector(13 downto 0); iamge_ana_state :out std_logic_vector(7 downto 0); test : out STD_LOGIC_VECTOR (4 downto 0)); end iamge_ana; architectureBehavioral of iamge_ana is signal clk_7M5:std_logic; signal cnt_7M5:integer range 0 to 7; signal addra_ana_buf:std_logic_vector(16downto 0); signal cnt_h:integer range 0 to 511; signalena_ana_buf:std_logic; signal cnt_p:std_logic_vector(8 downto 0); signaldina_ana_buf:std_logic_vector(13 downto 0); begin test(0)<=clk_7M5; test(1)<=ena_ana_buf; test(2)<=HORI; test(3)<=VERT; test(4)<=addra_ana_buf(0); iamge_ana_state<="0000000"&LOS; start_ana<='1' when VERT='0' andODD_EVEN='1' else '0'; addra_ana<=addra_ana_buf; ena_ana<=ena_ana_buf; AD_CLK<=clk_7M5; clk_ana<=not clk_7M5; process(clk_7M5) begin if rising_edge(clk_7M5) then dina_ana<=AD_D;--dina_ana_buf;-- end if; end process; process(lock,clk_in) begin if lock='0' then cnt_7M5<=0; clk_7M5<='0'; elsif rising_edge(clk_in) then if cnt_7M5=7 then cnt_7M5<=0; else cnt_7M5<=cnt_7M5+1; end if; if cnt_7M5<4 then clk_7M5<='0'; else clk_7M5<='1'; end if; end if; end process; process(VERT,HORI) begin if VERT='0' then cnt_h<=0; elsif rising_edge(HORI) then cnt_h<=cnt_h+1; end if; end process; process(HORI,clk_7M5) begin if HORI='0' then cnt_p<=(others=>'0'); elsif falling_edge(clk_7M5) then cnt_p<=cnt_p+1; end if; end process; process(clk_7M5) begin if rising_edge(clk_7M5) then if (cnt_h>21 andcnt_h<=309) and HORI='1' and ODD_EVEN='1' and (cnt_p>65 andcnt_p<=449) then ena_ana_buf<='1'; if dina_ana_buf=255then dina_ana_buf<=(others=>'0'); else dina_ana_buf<=dina_ana_buf+1; end if; else ena_ana_buf<='0'; dina_ana_buf<=(others=>'0'); end if; end if; end process; process(VERT,clk_7M5) begin if VERT='0' then addra_ana_buf<=(others=>'0'); elsif rising_edge(clk_7M5) then if ena_ana_buf='1' andODD_EVEN='1' then ifaddra_ana_buf=110591 then addra_ana_buf<=(others=>'0'); else addra_ana_buf<=addra_ana_buf+1; end if; end if; end if; end process; end Behavioral; O(∩_∩)O谢谢了 0 已退回1积分
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