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乘法模块: library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; port( clk : in std_logic; reset: in std_logic; data : in std_logic_vector(7 downto 0); data_pn : in std_logic; res : in std_logic_vector(27 downto 0); res_pn: in std_logic; data1: out std_logic_vector(27 downto 0); data2: out std_logic_vector(7 downto 0); data1_pn:out std_logic; data2_pn:out std_logic ); end entity mul; architecture behave of mul is signal temp1:std_logic; signal temp2:std_logic; begin process(reset,clk) begin if(reset='0')then if(clk'event and clk='1')then data1<=res; data1_pn<=res_pn; end if; if(clk'event and clk='0')then data2<=data; data2_pn<=data_pn; end if; else data1<="0000000000000000000000000000";data2<="00000000"; end if; end process; end behave; 除法模块: library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity div is port( clk : in std_logic; reset: in std_logic; data : in std_logic_vector(7 downto 0); data_pn : in std_logic; res : in std_logic_vector(27 downto 0); res_pn: in std_logic; data1: out std_logic_vector(27 downto 0); data2: out std_logic_vector(7 downto 0); data1_pn:out std_logic; data2_pn:out std_logic ); end entity div; architecture behave of div is signal temp1:std_logic; signal temp2:std_logic; begin process(reset,clk) begin if(reset='0')then if(clk'event and clk='1')then data1<=res; data1_pn<=res_pn; end if; if(clk'event and clk='0')then data2<=data; data2_pn<=data_pn; end if; else data1<="0000000000000000000000000000";data2<="00000000"; end if; end process; end behave; 乘或除数据选择输出模块: library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity tt is port( reset:in std_logic; pn1:in std_logic; pn2:in std_logic; res1:in std_logic_vector(27 downto 0 ); res2:in std_logic_vector(27 downto 0 ); clk1: in std_logic; clk2: in std_logic; resout: out std_logic_vector(27 downto 0 ); pnout:out std_logic; dout:out std_logic ); end entity tt; architecture behave of tt is signal temp:std_logic; begin dout<=temp; process(clk1,clk2) begin if(reset='0')then if(clk1='1')then temp<='0'; elsif(clk2'event and clk2='0')then temp<='1'; end if; if(temp='1')then resout<=res2;pnout<=pn2; else resout<=res1;pnout<=pn1; end if; else temp<='0'; end if; end process; end behave; 结果反馈及输出模块: library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity res_cs is port( reset:in std_logic; data: in std_logic_vector(7 downto 0); data_pn: in std_logic; clr: in std_logic; clk: in std_logic; res: in std_logic_vector(27 downto 0); res_pn:in std_logic; result: out std_logic_vector(27 downto 0); result_pn:out std_logic ); end entity res_cs; architecture behave of res_cs is signal cn:std_logic_vector(3 downto 0); begin process(clk,clr) begin if(reset='0')then if(clr='0')then if(cn="0000")then result<="0000000000000"&(data*"1100100");result_pn<=data_pn; else result<=res;result_pn<=res_pn; end if; if(clk'event and clk='1')then cn<=cn+1; end if; else cn<="0000"; end if; else cn<="0000"; end if; end process; end behave; 加减选择模块: library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity tt2 is port( reset:in std_logic; pn:in std_logic; clk1: in std_logic; clk2: in std_logic; pnout:out std_logic; dout:out std_logic ); end entity tt2; architecture behave of tt2 is signal temp:std_logic; begin dout<=temp; process(clk1,clk2) begin if(reset='0')then if(clk1='1')then temp<='0'; elsif(clk2'event and clk2='0')then temp<='1'; end if; if(temp='1')then pnout<=not(pn); else pnout<=pn; end if; else temp<='0'; end if; end process; end behave; 加减运算模块: library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity add is port(clk :in std_logic; reset:in std_logic; data:in std_logic_vector(27 downto 0); data_pn:in std_logic; dout :out std_logic_vector(27 downto 0); dout_pn:out std_logic ); end entity add; architecture behave of add is signal temp: std_logic_vector(27 downto 0):="0000000000000000000000000000"; signal temp_pn:std_logic:='0'; begin dout<=temp; dout_pn<=temp_pn; process(clk,reset) begin if(reset='1')then temp<="0000000000000000000000000000";temp_pn<='0'; elsif(clk'event and clk='1')then if(temp_pn='0')then if(data_pn='0')then temp<=temp+data;temp_pn<='0'; else if(temp>data or temp=data)then temp<=temp-data;temp_pn<='0'; else temp<=data-temp;temp_pn<='1'; end if; end if; else if(data_pn='1')then temp<=temp+data;temp_pn<='1'; else if(temp else temp<=temp-data;temp_pn<='1'; end if; end if; end if; end if; end process; end behave; 数据输出选择模块: library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity choose_out is port( reset: in std_logic; equal : in std_logic; data: in std_logic_vector(7 downto 0); data_pn : in std_logic; res : in std_logic_vector(27 downto 0); res_pn: in std_logic; result:out std_logic_vector(27 downto 0); result_pn:out std_logic_vector(3 downto 0)--正输出E 负输出F 溢出输出C ); end entity choose_out; architecture behave of choose_out is begin process(reset,equal) begin if(reset='0')then if(equal='0')then result<="00000000000000000000"&data; if(data_pn='0')then result_pn<="1110"; else result_pn<="1111"; end if; else if(res>"100110001001011001111111")then result<="0000000000000000000000000000";result_pn<="1100"; else result<=res; if(res_pn='0')then result_pn<="1110"; else result_pn<="1111"; end if; end if; end if; else result<="0000000000000000000000000000";result_pn<="0000"; end if; end process; end behave; 数据输入模块: library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity leijia is port( reset:in std_logic; clk: in std_logic; dataout: out std_logic_vector(7 downto 0) ); end entity leijia; architecture behave of leijia is signal temp:std_logic_vector(7 downto 0); begin dataout<=temp; process(clk,reset) begin if(reset='0')then if(clk'event and clk='1')then if(temp="01100100")then temp<="00000000"; else temp<=temp+1; end if; end if; else temp<="00000000"; end if; end process; end behave;
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