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本帖最后由 xuzhihua1209 于 2014-11-2 20:03 编辑
//------------------------------------------------------------- // Designer : W // Date : 2008.12.16 // Discription :Cordic with computation of modulus and angle. //------------------------------------------------------------- module fft_cordic( dout_i, dout_q, din_i, din_q, target_ang, clk, rst ); //parameters definations parameter INPUT_WIDTH =16;//signed fractioanl [1].[15] parameter INTERNAL_WIDTH =17;//signed fractioanl [2].[15] parameter OUTPUT_WIDTH =17;//signed fractioanl [2].[15] parameter ANGLE_WIDTH =32;//signed fractioanl [10].[22] parameter ITERATION =16;//Up to 16 mostly //cordic angles parameter atan_inf = 32'b0001011010_0000000000000000000000; parameter atan_1_1 = 32'b0000101101_0000000000000000000000; parameter atan_1_2 = 32'b0000011010_1001000010100111001100; parameter atan_1_4 = 32'b0000001110_0000100101000111010000; parameter atan_1_8 = 32'b0000000111_0010000000000001000100; parameter atan_1_16 = 32'b0000000011_1001001110001010101001; parameter atan_1_32 = 32'b0000000001_1100101000110111100101; parameter atan_1_64 = 32'b0000000000_1110010100101010000110; parameter atan_1_128 = 32'b0000000000_0111001010010110110101; parameter atan_1_256 = 32'b0000000000_0011100101001011101001; parameter atan_1_512 = 32'b0000000000_0001110010100101110110; parameter atan_1_1024 = 32'b0000000000_0000111001010010111011; parameter atan_1_2048 = 32'b0000000000_0000011100101001011101; parameter atan_1_4096 = 32'b0000000000_0000001110010100101110; parameter atan_1_8192 = 32'b0000000000_0000000111001010010111; parameter atan_1_16384 = 32'b0000000000_0000000011100101001011; parameter atan_1_32768 = 32'b0000000000_0000000001110010100101; //integers integer stage; integer signext; //extend output width to avoid overflow output [(OUTPUT_WIDTH-1):0] dout_i; //signed fractioanl [2].[15] output [(OUTPUT_WIDTH-1):0] dout_q; //signed fractioanl [2].[15] input [(INPUT_WIDTH-1):0] din_i; //signed fractional [1].[15] input [(INPUT_WIDTH-1):0] din_q; //signed fractional [1].[15] input [(ANGLE_WIDTH-1):0] target_ang;//signed fractional [10].[22] input clk; //149MHz in 2C device;166MHz in 3C device input rst; //active hign reset //reg reg [(INTERNAL_WIDTH-1):0] din_i_pipe[0:ITERATION]; //register reg [(INTERNAL_WIDTH-1):0] din_q_pipe[0:ITERATION]; //register reg [(ANGLE_WIDTH-1):0] ang_accum[0:ITERATION]; //register reg [(INTERNAL_WIDTH-1):0] x_shift_wire; //combinational wire reg [(INTERNAL_WIDTH-1):0] y_shift_wire; //combinational wire reg [(ANGLE_WIDTH-1):0] current_angle; //internal wire //wire wire [(OUTPUT_WIDTH-1):0] dout_i; //output wire wire [(OUTPUT_WIDTH-1):0] dout_q; //output wire //extend output width to avoid overflow assign dout_i = din_i_pipe[ITERATION];//connect the ouput wire to the last interation reg assign dout_q = din_q_pipe[ITERATION];//connect the ouput wire to the last interation reg // always @(posedge clk or posedge rst) if (rst) //reset all register for (stage=0; stage<=ITERATION; stage=stage+1) begin din_i_pipe[stage] <= {INTERNAL_WIDTH{1'b0}}; din_q_pipe[stage] <= {INTERNAL_WIDTH{1'b0}}; ang_accum[stage] <= {ANGLE_WIDTH{1'b0}}; end else begin //extend 1-bit to avoid internal result overflow din_i_pipe[0] <={din_i[INPUT_WIDTH-1],din_i}; din_q_pipe[0] <={din_q[INPUT_WIDTH-1],din_q}; //cordic iterations (45 26.56 14.03 7.12 ... degree rotaions) for (stage=1; stage<=ITERATION; stage=stage+1) begin //(not generally good practice to mix blocking and non-blocking assignments in same process) // define rotaion angle in the current iteration case(stage) 1: current_angle=atan_1_1; 2: current_angle=atan_1_2; 3: current_angle=atan_1_4; 4: current_angle=atan_1_8; 5: current_angle=atan_1_16; 6: current_angle=atan_1_32; 7: current_angle=atan_1_64; 8: current_angle=atan_1_128; 9: current_angle=atan_1_256; 10: current_angle=atan_1_512; 11: current_angle=atan_1_1024; 12: current_angle=atan_1_2048; 13: current_angle=atan_1_4096; 14: current_angle=atan_1_8192; 15: current_angle=atan_1_16384; 16: current_angle=atan_1_32768; endcase //shift right and reserve the sign x_shift_wire = din_i_pipe[stage-1] >> (stage-1); y_shift_wire = din_q_pipe[stage-1] >> (stage-1); for (signext=(INTERNAL_WIDTH-stage); signext < INTERNAL_WIDTH;signext=signext + 1) begin x_shift_wire[signext] = din_i_pipe[stage-1][(INTERNAL_WIDTH-1)]; y_shift_wire[signext] = din_q_pipe[stage-1][(INTERNAL_WIDTH-1)]; end //cordic equations if (ang_accum[stage-1]>target_ang) begin din_i_pipe[stage] <= din_i_pipe[stage-1]-y_shift_wire; din_q_pipe[stage] <= din_q_pipe[stage-1]+x_shift_wire; ang_accum[stage] <= ang_accum[stage-1] + (~current_angle+{{(ANGLE_WIDTH-1){1'b0}},1'b1} ); end else begin din_i_pipe[stage] <= din_i_pipe[stage-1]+y_shift_wire; din_q_pipe[stage] <= din_q_pipe[stage-1]-x_shift_wire; ang_accum[stage] <= ang_accum[stage-1] + current_angle; end end//'for' end end //'else' end endmodule 程序编译正确,能够在Quartus中生成模块电路图,但是图形仿真有点问题,还请大神指导一下。 |
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