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第一段程序:
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENtiTY pwmgen IS generic ( f_len:natural:=9; delay_len:natural:=9; dead:natural:=5 ); port( rst,clk:in std_logic; feedin:in std_logic; di:in std_logic; --delay:in std_logic_vector(f_len-1 downto 0); pwm1,pwm3,pwm2,pwm4:out std_logic ); end entity pwmgen ; architecture bhv of pwmgen is signal tm,pwm10,pwm20,pwm30,pwm40:std_logic; signal delay_r:std_logic_vector(delay_len+f_len-1 downto 0); signal cmp,cmp_dead:std_logic_vector(f_len-1 downto 0); signal f,fi:std_logic_vector(f_len-1 downto 0); signal delay:std_logic_vector(f_len-1 downto 0):="011001100"; signal feedcount:std_logic_vector(11 downto 0):="000000000000"; signal close:std_logic:='0'; signal dis: std_logic; component fcounter generic ( f_len:natural:=9; f_delta:natural:=10 ); port( rst,clk,di:in std_logic; f,fi:out std_logic_vector(f_len-1 downto 0); tm:out std_logic ); end component; begin d1:process(clk,close) begin if close='0' then if clk'event and clk='1' then if feedcount<"111111111100" then feedcount<=feedcount+'1'; dis<=di; -- di1<=dis; else close<='1'; dis<=feedin; -- di1<=dis; end if; end if; else dis<=feedin; -- di1<=dis; end if; end process; fc1:fcounter generic map(9,10) port map(rst,clk,dis,f,fi,tm); delay_r<=delay*f; cmp<=delay_r(delay_len+f_len-1 downto delay_len); cmp_dead<="0"&f(f'length-1 downto 1)-dead; --adad d:process(clk,rst) begin if rst='0' then pwm10<='0'; pwm20<='0'; pwm30<='0'; pwm40<='0'; elsif clk'event and clk='1' then if (fi>=0 and fi if tm='0' then pwm20<='1';end if; else pwm10<='0'; pwm20<='0'; end if; if (fi>dead and fi if tm='0' then pwm40<='1';end if; else pwm30<='0'; pwm40<='0'; end if; end if; end process; pwm1<=pwm10 and pwm30; pwm3<=pwm20 and pwm40; pwm2<=not dis; pwm4<=dis; end bhv; |
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4个回答
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第二段程序:
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; entity fcounter is generic ( f_len:natural:=9; --棰戠巼鏈€澶***鏁 f_delta:natural:=10 ); port( rst,clk,di:in std_logic; f,fi:out std_logic_vector(f_len-1 downto 0); tm:out std_logic ); end entity fcounter ; architecture bhv of fcounter is type f_reg_type is array (natural range<>) of std_logic_vector(f_len-1 downto 0); signal f_reg:f_reg_type(2+2 downto 0); signal fsum:std_logic_vector(f_len-1+2 downto 0); signal di_reg:std_logic_vector(3 downto 0); signal di_rise,di_fall:std_logic; signal cnt:std_logic_vector(f_len-1 downto 0); begin fsum<="00"&f_reg(0)+f_reg(1)+f_reg(2)+f_reg(2); f<=fsum(f_len-1+2 downto 2); fi<=cnt; count:process(clk,rst) begin if rst='0' then di_reg<=(others=>'0'); f_reg<=(others=>(others=>'0')); cnt<=(others=>'0'); tm<='0'; elsif clk'event and clk='1' then cnt<=cnt+'1'; di_reg<=di_reg(2 downto 0)&di; if di_rise='1' then f_reg(4)<=cnt; cnt<=(others=>'0'); tm<='1'; end if; if di_fall='1' then f_reg(3)<=cnt; cnt<=(others=>'0'); tm<='0'; end if; if (f_reg(3)>f_reg(4) and f_reg(3)-f_delta f_reg(2 downto 0)<=f_reg(1 downto 0)&(f_reg(3)+f_reg(4)); end if; end if; end process; di_rise<= '1' when (di_reg(2)='0' and di_reg(1)='0'and di_reg(0)='1' and di='1') else '0'; di_fall<= '1' when (di_reg(2)='1' and di_reg(1)='1'and di_reg(0)='0' and di='0') else '0'; end bhv; |
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仿真时为什么pwm1和pwm3 没有输出波形呢?请前辈们指教啊
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这几天也在琢磨PWM,看半天,还是没有看懂你的程序
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没有看懂,等待大神来解释了
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求FPGA 驱动控制ltc2271 或者 ltc2180 或者 ltc2190或者 ltc2202 的代码
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求助:遇见诡异问题,FPGA模块A输出端口连接模块B输入后,模块A不能正常工作的
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