Verilog秒表程序在lcd上显示秒表正常但画面一直往右跑

ti

如题，整个画面都一直往右跑，间隔有8个字符，而且还是两行都显示秒表，程序如下：
module clock(clk,rst,lcd_rs,lcd_rw,lcd_en,lcd_data);
input clk,rst;
output lcd_en,lcd_rw,lcd_rs;
output[7:0] lcd_data;
reg lcd_rs,lcd_rw;
reg[7:0] lcd_data;

parameter IDLE          =4'd0;
parameter CLEAR       =4'd1;
parameter SET_FUNCtiON =4'd2;
parameter SWITCH_MODE =4'd3;
parameter SET_MODE    =4'd4;
parameter SET_DDRAM    =4'd5;
parameter WRITE_RAM    =4'd6;
parameter SHIFT       =4'd7;
parameter STOP          =4'd8;

reg[17:0] count;
reg clk_buf;
always@(posedge clk or negedge rst)
   if(!rst)
      begin
   clk_buf<=0;
count<=0;
   end
   else if(count<=125000)
         begin
         clk_buf<=0;
count<=count+1;
   end
   else if(count>250000-1)
         count<=0;
else
   begin
   clk_buf<=1;
   count<=count+1;
   end
assign lcd_en=clk_buf;

reg[7:0] clock_second_l;
reg[7:0] clock_second_h;
reg[7:0] clock_minute_l;
reg[7:0] clock_minute_h;
reg[7:0] clock_hour_l;
reg[7:0] clock_hour_h;
reg[31:0] counter;

initial
begin
   clock_second_l<=8'h30;
   clock_second_h<=8'h30;
   clock_minute_l<=8'h30;
   clock_minute_h<=8'h30;
   clock_hour_l<=8'h30;
   clock_hour_h<=8'h30;
   counter<=0;
end

always@(posedge clk or negedge rst)
   begin
   if(rst==0)
   begin
         clock_second_l<=8'h30;
         clock_second_h<=8'h30;
         clock_minute_l<=8'h30;
         clock_minute_h<=8'h30;
         clock_hour_l<=8'h30;
         clock_hour_h<=8'h30;
   counter<=0;
   end
else  if(counter==50_000_000)
               begin
               clock_second_l<=clock_second_l+1'b1;
         counter<=0;
         end
else if(clock_second_l==8'h3A)
   begin
   clock_second_h<=clock_second_h+1'b1;
   clock_second_l<=8'h30;
   counter<=counter+1'b1;
   end
else if(clock_second_h==8'h36)
   begin
   clock_minute_l<=clock_minute_l+1'b1;
   clock_second_h<=8'h30;
   counter<=counter+1'b1;
   end
else if(clock_minute_l==8'h3A)
   begin
   clock_minute_h<=clock_minute_h+1'b1;
   clock_minute_l<=8'h30;
   counter<=counter+1'b1;
   end
else if(clock_minute_h==8'h36)
               begin
            clock_hour_l<=clock_hour_l+1'b1;
   clock_minute_h<=8'h30;
   counter<=counter+1'b1;
   end
else if(clock_hour_l==8'h3A)
               begin
   clock_hour_h<=clock_hour_h+1'b1;
   clock_hour_l<=8'h30;
   counter<=counter+1'b1;
   end
else if(clock_hour_h==8'h32)
            begin
               if(clock_hour_l==8'h34)
   begin
   clock_second_l<=8'h30;
               clock_second_h<=8'h30;
               clock_minute_l<=8'h30;
                  clock_minute_h<=8'h30;
               clock_hour_l<=8'h30;
                  clock_hour_h<=8'h30;
            counter<=0;
   end
end
else  counter<=counter+1'b1;
   end

reg[7:0] data[15:0];
always@(posedge clk_buf)
   begin
   data[0]=" ";
   data[1]=" ";
      data[2]=" ";
         data[3]=" ";
      data[4]<=clock_hour_h;//时针高位
   data[5]<=clock_hour_l;//时针低位
   data[6]=":";
   data[7]<=clock_minute_h;//分针高位
   data[8]<=clock_minute_l;//分针低位
   data[9]=":";
   data[10]<=clock_second_h;//秒针高位
   data[11]<=clock_second_l;//秒针低位
   data[12]=" ";
   data[13]=" ";
   data[14]=" ";
   data[15]=" ";
   end


reg[3:0] state;
reg[6:0] address;

always@(posedge clk_buf or negedge rst)
   if(rst==0)
   begin
      state<=IDLE;
   lcd_data<=8'b0000_0000;
   lcd_rs<=0;
   lcd_rw<=0;
   address<=0;
   end
else
   begin
      case(state)
   IDLE:
         begin
      lcd_rs<=0;
         lcd_rw<=0;
   lcd_data<=8'b0000_0000;
   state<=CLEAR;
   end
      CLEAR:
         begin
   lcd_rs<=0;
         lcd_rw<=0;
   lcd_data<=8'b0000_0001;
   state<=SET_FUNCTION;
   end
SET_FUNCTION:
               begin
   lcd_rs<=0;
         lcd_rw<=0;
   lcd_data<=8'b0011_1000;//0011_1000
   state<=SWITCH_MODE;
   end
      SWITCH_MODE:
               begin
   lcd_rs<=0;
         lcd_rw<=0;
   lcd_data<=8'b0000_1111;
   state<=SET_MODE;
   end
      SET_MODE:
            begin
   lcd_rs<=0;
         lcd_rw<=0;
   lcd_data<=8'b0000_0110;
   state<=SHIFT;
   end
   SHIFT:
         begin
   lcd_rs<=0;
         lcd_rw<=0;
   lcd_data<=8'b0001_0100;
   state<=SET_DDRAM;
   end
   SET_DDRAM:
            begin
   lcd_rs<=0;
         lcd_rw<=0;
   lcd_data<=8'b1000_0000;
   address<=0;
   state<=WRITE_RAM;
   end
   WRITE_RAM:
            begin
   if(address<=15)
   begin
      lcd_rs<=1;
   lcd_rw<=0;
   lcd_data<=data[address];
   address<=address+1'b1;
     // state<=WRITE_RAM;
   end
   else
   begin
      address<=0;
   state<=WRITE_RAM;
   end
   end

      STOP:
         begin
   state<=STOP;
address<=0;
lcd_rw<=1;
   end
   default:  state<=CLEAR;
   endcase
   end
endmodule

yyiverson · 2014-7-25 22:21:30

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Verilog秒表程序 在lcd上显示 秒表正常 但画面一直往右跑

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Verilog秒表程序在lcd上显示秒表正常但画面一直往右跑