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/* */ /* Flexible Static Memory Controller */这里是源文件 /* */ /******************************************************************************/ /****************** Bit definition for FSMC_BCR1 register *******************/ #define FSMC_BCR1_MBKEN ((uint32_t)0x00000001) /*!< Memory bank enable bit */ #define FSMC_BCR1_MUXEN ((uint32_t)0x00000002) /*!< Address/data multiplexing enable bit */ #define FSMC_BCR1_MTYP ((uint32_t)0x0000000C) /*!< MTYP[1:0] bits (Memory type) */ #define FSMC_BCR1_MTYP_0 ((uint32_t)0x00000004) /*!< Bit 0 */ #define FSMC_BCR1_MTYP_1 ((uint32_t)0x00000008) /*!< Bit 1 */ #define FSMC_BCR1_MWID ((uint32_t)0x00000030) /*!< MWID[1:0] bits (Memory data bus width) */ #define FSMC_BCR1_MWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */ #define FSMC_BCR1_MWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */ #define FSMC_BCR1_FACCEN ((uint32_t)0x00000040) /*!< Flash access enable */ #define FSMC_BCR1_BURSTEN ((uint32_t)0x00000100) /*!< Burst enable bit */ #define FSMC_BCR1_WAITPOL ((uint32_t)0x00000200) /*!< Wait signal polarity bit */ #define FSMC_BCR1_WRAPMOD ((uint32_t)0x00000400) /*!< Wrapped burst mode support */ #define FSMC_BCR1_WAITCFG ((uint32_t)0x00000800) /*!< Wait timing configuration */ #define FSMC_BCR1_WREN ((uint32_t)0x00001000) /*!< Write enable bit */ #define FSMC_BCR1_WAITEN ((uint32_t)0x00002000) /*!< Wait enable bit */ #define FSMC_BCR1_EXTMOD ((uint32_t)0x00004000) /*!< Extended mode enable */ #define FSMC_BCR1_ASYNCWAIT ((uint32_t)0x00008000) /*!< Asynchronous wait */ #define FSMC_BCR1_CBURSTRW ((uint32_t)0x00080000) /*!< Write burst enable */ /****************** Bit definition for FSMC_BCR2 register *******************/ #define FSMC_BCR2_MBKEN ((uint32_t)0x00000001) /*!< Memory bank enable bit */ #define FSMC_BCR2_MUXEN ((uint32_t)0x00000002) /*!< Address/data multiplexing enable bit */ #define FSMC_BCR2_MTYP ((uint32_t)0x0000000C) /*!< MTYP[1:0] bits (Memory type) */ #define FSMC_BCR2_MTYP_0 ((uint32_t)0x00000004) /*!< Bit 0 */ #define FSMC_BCR2_MTYP_1 ((uint32_t)0x00000008) /*!< Bit 1 */ #define FSMC_BCR2_MWID ((uint32_t)0x00000030) /*!< MWID[1:0] bits (Memory data bus width) */ #define FSMC_BCR2_MWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */ #define FSMC_BCR2_MWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */ #define FSMC_BCR2_FACCEN ((uint32_t)0x00000040) /*!< Flash access enable */ #define FSMC_BCR2_BURSTEN ((uint32_t)0x00000100) /*!< Burst enable bit */ #define FSMC_BCR2_WAITPOL ((uint32_t)0x00000200) /*!< Wait signal polarity bit */ #define FSMC_BCR2_WRAPMOD ((uint32_t)0x00000400) /*!< Wrapped burst mode support */ #define FSMC_BCR2_WAITCFG ((uint32_t)0x00000800) /*!< Wait timing configuration */ #define FSMC_BCR2_WREN ((uint32_t)0x00001000) /*!< Write enable bit */ #define FSMC_BCR2_WAITEN ((uint32_t)0x00002000) /*!< Wait enable bit */ #define FSMC_BCR2_EXTMOD ((uint32_t)0x00004000) /*!< Extended mode enable */ #define FSMC_BCR2_ASYNCWAIT ((uint32_t)0x00008000) /*!< Asynchronous wait */ #define FSMC_BCR2_CBURSTRW ((uint32_t)0x00080000) /*!< Write burst enable */ /****************** Bit definition for FSMC_BCR3 register *******************/ #define FSMC_BCR3_MBKEN ((uint32_t)0x00000001) /*!< Memory bank enable bit */ #define FSMC_BCR3_MUXEN ((uint32_t)0x00000002) /*!< Address/data multiplexing enable bit */ #define FSMC_BCR3_MTYP ((uint32_t)0x0000000C) /*!< MTYP[1:0] bits (Memory type) */ #define FSMC_BCR3_MTYP_0 ((uint32_t)0x00000004) /*!< Bit 0 */ #define FSMC_BCR3_MTYP_1 ((uint32_t)0x00000008) /*!< Bit 1 */ #define FSMC_BCR3_MWID ((uint32_t)0x00000030) /*!< MWID[1:0] bits (Memory data bus width) */ #define FSMC_BCR3_MWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */ #define FSMC_BCR3_MWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */ #define FSMC_BCR3_FACCEN ((uint32_t)0x00000040) /*!< Flash access enable */ #define FSMC_BCR3_BURSTEN ((uint32_t)0x00000100) /*!< Burst enable bit */ #define FSMC_BCR3_WAITPOL ((uint32_t)0x00000200) /*!< Wait signal polarity bit. */ #define FSMC_BCR3_WRAPMOD ((uint32_t)0x00000400) /*!< Wrapped burst mode support */ #define FSMC_BCR3_WAITCFG ((uint32_t)0x00000800) /*!< Wait timing configuration */ #define FSMC_BCR3_WREN ((uint32_t)0x00001000) /*!< Write enable bit */ #define FSMC_BCR3_WAITEN ((uint32_t)0x00002000) /*!< Wait enable bit */ #define FSMC_BCR3_EXTMOD ((uint32_t)0x00004000) /*!< Extended mode enable */ #define FSMC_BCR3_ASYNCWAIT ((uint32_t)0x00008000) /*!< Asynchronous wait */ #define FSMC_BCR3_CBURSTRW ((uint32_t)0x00080000) /*!< Write burst enable */ /****************** Bit definition for FSMC_BCR4 register *******************/ #define FSMC_BCR4_MBKEN ((uint32_t)0x00000001) /*!< Memory bank enable bit */ #define FSMC_BCR4_MUXEN ((uint32_t)0x00000002) /*!< Address/data multiplexing enable bit */ #define FSMC_BCR4_MTYP ((uint32_t)0x0000000C) /*!< MTYP[1:0] bits (Memory type) */ #define FSMC_BCR4_MTYP_0 ((uint32_t)0x00000004) /*!< Bit 0 */ #define FSMC_BCR4_MTYP_1 ((uint32_t)0x00000008) /*!< Bit 1 */ #define FSMC_BCR4_MWID ((uint32_t)0x00000030) /*!< MWID[1:0] bits (Memory data bus width) */ #define FSMC_BCR4_MWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */ #define FSMC_BCR4_MWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */ #define FSMC_BCR4_FACCEN ((uint32_t)0x00000040) /*!< Flash access enable */ #define FSMC_BCR4_BURSTEN ((uint32_t)0x00000100) /*!< Burst enable bit */ #define FSMC_BCR4_WAITPOL ((uint32_t)0x00000200) /*!< Wait signal polarity bit */ #define FSMC_BCR4_WRAPMOD ((uint32_t)0x00000400) /*!< Wrapped burst mode support */ #define FSMC_BCR4_WAITCFG ((uint32_t)0x00000800) /*!< Wait timing configuration */ #define FSMC_BCR4_WREN ((uint32_t)0x00001000) /*!< Write enable bit */ #define FSMC_BCR4_WAITEN ((uint32_t)0x00002000) /*!< Wait enable bit */ #define FSMC_BCR4_EXTMOD ((uint32_t)0x00004000) /*!< Extended mode enable */ #define FSMC_BCR4_ASYNCWAIT ((uint32_t)0x00008000) /*!< Asynchronous wait */ #define FSMC_BCR4_CBURSTRW ((uint32_t)0x00080000) /*!< Write burst enable */ /****************** Bit definition for FSMC_BTR1 register ******************/ #define FSMC_BTR1_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ #define FSMC_BTR1_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ #define FSMC_BTR1_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ #define FSMC_BTR1_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ #define FSMC_BTR1_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ #define FSMC_BTR1_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ #define FSMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ #define FSMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ #define FSMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ #define FSMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ #define FSMC_BTR1_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ #define FSMC_BTR1_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ #define FSMC_BTR1_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ #define FSMC_BTR1_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ #define FSMC_BTR1_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ #define FSMC_BTR1_BUSTURN ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */ #define FSMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!< Bit 0 */ #define FSMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000) /*!< Bit 1 */ #define FSMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000) /*!< Bit 2 */ #define FSMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000) /*!< Bit 3 */ #define FSMC_BTR1_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ #define FSMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ #define FSMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ #define FSMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ #define FSMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ #define FSMC_BTR1_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ #define FSMC_BTR1_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ #define FSMC_BTR1_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ #define FSMC_BTR1_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ #define FSMC_BTR1_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ #define FSMC_BTR1_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ #define FSMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ #define FSMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ /****************** Bit definition for FSMC_BTR2 register *******************/ #define FSMC_BTR2_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ #define FSMC_BTR2_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ #define FSMC_BTR2_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ #define FSMC_BTR2_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ #define FSMC_BTR2_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ #define FSMC_BTR2_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ #define FSMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ #define FSMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ #define FSMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ #define FSMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ #define FSMC_BTR2_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ #define FSMC_BTR2_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ #define FSMC_BTR2_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ #define FSMC_BTR2_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ #define FSMC_BTR2_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ #define FSMC_BTR2_BUSTURN ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */ #define FSMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!< Bit 0 */ #define FSMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000) /*!< Bit 1 */ #define FSMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000) /*!< Bit 2 */ #define FSMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000) /*!< Bit 3 */ #define FSMC_BTR2_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ #define FSMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ #define FSMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ #define FSMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ #define FSMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ #define FSMC_BTR2_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ #define FSMC_BTR2_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ #define FSMC_BTR2_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ #define FSMC_BTR2_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ #define FSMC_BTR2_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ #define FSMC_BTR2_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ #define FSMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ #define FSMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ /******************* Bit definition for FSMC_BTR3 register *******************/ #define FSMC_BTR3_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ #define FSMC_BTR3_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ #define FSMC_BTR3_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ #define FSMC_BTR3_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ #define FSMC_BTR3_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ #define FSMC_BTR3_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ #define FSMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ #define FSMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ #define FSMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ #define FSMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ #define FSMC_BTR3_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ #define FSMC_BTR3_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ #define FSMC_BTR3_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ #define FSMC_BTR3_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ #define FSMC_BTR3_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ #define FSMC_BTR3_BUSTURN ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */ #define FSMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!< Bit 0 */ #define FSMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000) /*!< Bit 1 */ #define FSMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000) /*!< Bit 2 */ #define FSMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000) /*!< Bit 3 */ #define FSMC_BTR3_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ #define FSMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ #define FSMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ #define FSMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ #define FSMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ #define FSMC_BTR3_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ #define FSMC_BTR3_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ #define FSMC_BTR3_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ #define FSMC_BTR3_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ #define FSMC_BTR3_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ #define FSMC_BTR3_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ #define FSMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ #define FSMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ /****************** Bit definition for FSMC_BTR4 register *******************/ #define FSMC_BTR4_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ #define FSMC_BTR4_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ #define FSMC_BTR4_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ #define FSMC_BTR4_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ #define FSMC_BTR4_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ #define FSMC_BTR4_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ #define FSMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ #define FSMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ #define FSMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ #define FSMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ #define FSMC_BTR4_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ #define FSMC_BTR4_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ #define FSMC_BTR4_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ #define FSMC_BTR4_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ #define FSMC_BTR4_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ #define FSMC_BTR4_BUSTURN ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */ #define FSMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!< Bit 0 */ #define FSMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000) /*!< Bit 1 */ #define FSMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000) /*!< Bit 2 */ #define FSMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000) /*!< Bit 3 */ #define FSMC_BTR4_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ #define FSMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ #define FSMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ #define FSMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ #define FSMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ #define FSMC_BTR4_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ #define FSMC_BTR4_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ #define FSMC_BTR4_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ #define FSMC_BTR4_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ #define FSMC_BTR4_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ #define FSMC_BTR4_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ #define FSMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ #define FSMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ /****************** Bit definition for FSMC_BWTR1 register ******************/ #define FSMC_BWTR1_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ #define FSMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ #define FSMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ #define FSMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ #define FSMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ #define FSMC_BWTR1_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ #define FSMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ #define FSMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ #define FSMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ #define FSMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ #define FSMC_BWTR1_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ #define FSMC_BWTR1_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ #define FSMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ #define FSMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ #define FSMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ #define FSMC_BWTR1_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ #define FSMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ #define FSMC_BWTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ #define FSMC_BWTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ #define FSMC_BWTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ #define FSMC_BWTR1_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ #define FSMC_BWTR1_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ #define FSMC_BWTR1_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ #define FSMC_BWTR1_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ #define FSMC_BWTR1_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ #define FSMC_BWTR1_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ #define FSMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ #define FSMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ /****************** Bit definition for FSMC_BWTR2 register ******************/ #define FSMC_BWTR2_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ #define FSMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ #define FSMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ #define FSMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ #define FSMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ #define FSMC_BWTR2_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ #define FSMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ #define FSMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ #define FSMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ #define FSMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ #define FSMC_BWTR2_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ #define FSMC_BWTR2_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ #define FSMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ #define FSMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ #define FSMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ #define FSMC_BWTR2_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ #define FSMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ #define FSMC_BWTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1*/ #define FSMC_BWTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ #define FSMC_BWTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ #define FSMC_BWTR2_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ #define FSMC_BWTR2_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ #define FSMC_BWTR2_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ #define FSMC_BWTR2_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ #define FSMC_BWTR2_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ #define FSMC_BWTR2_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ #define FSMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ #define FSMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ /****************** Bit definition for FSMC_BWTR3 register ******************/ #define FSMC_BWTR3_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ #define FSMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ #define FSMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ #define FSMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ #define FSMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ #define FSMC_BWTR3_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ #define FSMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ #define FSMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ #define FSMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ #define FSMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ #define FSMC_BWTR3_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ #define FSMC_BWTR3_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ #define FSMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ #define FSMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ #define FSMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ #define FSMC_BWTR3_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ #define FSMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ #define FSMC_BWTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ #define FSMC_BWTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ #define FSMC_BWTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ #define FSMC_BWTR3_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ #define FSMC_BWTR3_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ #define FSMC_BWTR3_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ #define FSMC_BWTR3_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ #define FSMC_BWTR3_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ #define FSMC_BWTR3_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ #define FSMC_BWTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ #define FSMC_BWTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ /****************** Bit definition for FSMC_BWTR4 register ******************/ #define FSMC_BWTR4_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ #define FSMC_BWTR4_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ #define FSMC_BWTR4_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ #define FSMC_BWTR4_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ #define FSMC_BWTR4_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ #define FSMC_BWTR4_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ #define FSMC_BWTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ #define FSMC_BWTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ #define FSMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ #define FSMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ #define FSMC_BWTR4_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ #define FSMC_BWTR4_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ #define FSMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ #define FSMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ #define FSMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ #define FSMC_BWTR4_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ #define FSMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ #define FSMC_BWTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ #define FSMC_BWTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ #define FSMC_BWTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ #define FSMC_BWTR4_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ #define FSMC_BWTR4_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ #define FSMC_BWTR4_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ #define FSMC_BWTR4_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ #define FSMC_BWTR4_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ #define FSMC_BWTR4_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ #define FSMC_BWTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ #define FSMC_BWTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ /****************** Bit definition for FSMC_PCR2 register *******************/ #define FSMC_PCR2_PWAITEN ((uint32_t)0x00000002) /*!< Wait feature enable bit */ #define FSMC_PCR2_PBKEN ((uint32_t)0x00000004) /*!< PC Card/NAND Flash memory bank enable bit */ #define FSMC_PCR2_PTYP ((uint32_t)0x00000008) /*!< Memory type */ #define FSMC_PCR2_PWID ((uint32_t)0x00000030) /*!< PWID[1:0] bits (NAND Flash databus width) */ #define FSMC_PCR2_PWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */ #define FSMC_PCR2_PWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */ #define FSMC_PCR2_ECCEN ((uint32_t)0x00000040) /*!< ECC computation logic enable bit */ #define FSMC_PCR2_TCLR ((uint32_t)0x00001E00) /*!< TCLR[3:0] bits (CLE to RE delay) */ #define FSMC_PCR2_TCLR_0 ((uint32_t)0x00000200) /*!< Bit 0 */ #define FSMC_PCR2_TCLR_1 ((uint32_t)0x00000400) /*!< Bit 1 */ #define FSMC_PCR2_TCLR_2 ((uint32_t)0x00000800) /*!< Bit 2 */ #define FSMC_PCR2_TCLR_3 ((uint32_t)0x00001000) /*!< Bit 3 */ #define FSMC_PCR2_TAR ((uint32_t)0x0001E000) /*!< TAR[3:0] bits (ALE to RE delay) */ #define FSMC_PCR2_TAR_0 ((uint32_t)0x00002000) /*!< Bit 0 */ #define FSMC_PCR2_TAR_1 ((uint32_t)0x00004000) /*!< Bit 1 */ #define FSMC_PCR2_TAR_2 ((uint32_t)0x00008000) /*!< Bit 2 */ #define FSMC_PCR2_TAR_3 ((uint32_t)0x00010000) /*!< Bit 3 */ #define FSMC_PCR2_ECCPS ((uint32_t)0x000E0000) /*!< ECCPS[1:0] bits (ECC page size) */ #define FSMC_PCR2_ECCPS_0 ((uint32_t)0x00020000) /*!< Bit 0 */ #define FSMC_PCR2_ECCPS_1 ((uint32_t)0x00040000) /*!< Bit 1 */ #define FSMC_PCR2_ECCPS_2 ((uint32_t)0x00080000) /*!< Bit 2 */ /****************** Bit definition for FSMC_PCR3 register *******************/ #define FSMC_PCR3_PWAITEN ((uint32_t)0x00000002) /*!< Wait feature enable bit */ #define FSMC_PCR3_PBKEN ((uint32_t)0x00000004) /*!< PC Card/NAND Flash memory bank enable bit */ #define FSMC_PCR3_PTYP ((uint32_t)0x00000008) /*!< Memory type */ #define FSMC_PCR3_PWID ((uint32_t)0x00000030) /*!< PWID[1:0] bits (NAND Flash databus width) */ #define FSMC_PCR3_PWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */ #define FSMC_PCR3_PWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */ #define FSMC_PCR3_ECCEN ((uint32_t)0x00000040) /*!< ECC computation logic enable bit */ #define FSMC_PCR3_TCLR ((uint32_t)0x00001E00) /*!< TCLR[3:0] bits (CLE to RE delay) */ #define FSMC_PCR3_TCLR_0 ((uint32_t)0x00000200) /*!< Bit 0 */ #define FSMC_PCR3_TCLR_1 ((uint32_t)0x00000400) /*!< Bit 1 */ #define FSMC_PCR3_TCLR_2 ((uint32_t)0x00000800) /*!< Bit 2 */ #define FSMC_PCR3_TCLR_3 ((uint32_t)0x00001000) /*!< Bit 3 */ #define FSMC_PCR3_TAR ((uint32_t)0x0001E000) /*!< TAR[3:0] bits (ALE to RE delay) */ #define FSMC_PCR3_TAR_0 ((uint32_t)0x00002000) /*!< Bit 0 */ #define FSMC_PCR3_TAR_1 ((uint32_t)0x00004000) /*!< Bit 1 */ #define FSMC_PCR3_TAR_2 ((uint32_t)0x00008000) /*!< Bit 2 */ #define FSMC_PCR3_TAR_3 ((uint32_t)0x00010000) /*!< Bit 3 */ #define FSMC_PCR3_ECCPS ((uint32_t)0x000E0000) /*!< ECCPS[2:0] bits (ECC page size) */ #define FSMC_PCR3_ECCPS_0 ((uint32_t)0x00020000) /*!< Bit 0 */ #define FSMC_PCR3_ECCPS_1 ((uint32_t)0x00040000) /*!< Bit 1 */ #define FSMC_PCR3_ECCPS_2 ((uint32_t)0x00080000) /*!< Bit 2 */ /****************** Bit definition for FSMC_PCR4 register *******************/ #define FSMC_PCR4_PWAITEN ((uint32_t)0x00000002) /*!< Wait feature enable bit */ #define FSMC_PCR4_PBKEN ((uint32_t)0x00000004) /*!< PC Card/NAND Flash memory bank enable bit */ #define FSMC_PCR4_PTYP ((uint32_t)0x00000008) /*!< Memory type */ #define FSMC_PCR4_PWID ((uint32_t)0x00000030) /*!< PWID[1:0] bits (NAND Flash databus width) */ #define FSMC_PCR4_PWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */ #define FSMC_PCR4_PWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */ #define FSMC_PCR4_ECCEN ((uint32_t)0x00000040) /*!< ECC computation logic enable bit */ #define FSMC_PCR4_TCLR ((uint32_t)0x00001E00) /*!< TCLR[3:0] bits (CLE to RE delay) */ #define FSMC_PCR4_TCLR_0 ((uint32_t)0x00000200) /*!< Bit 0 */ #define FSMC_PCR4_TCLR_1 ((uint32_t)0x00000400) /*!< Bit 1 */ #define FSMC_PCR4_TCLR_2 ((uint32_t)0x00000800) /*!< Bit 2 */ #define FSMC_PCR4_TCLR_3 ((uint32_t)0x00001000) /*!< Bit 3 */ #define FSMC_PCR4_TAR ((uint32_t)0x0001E000) /*!< TAR[3:0] bits (ALE to RE delay) */ #define FSMC_PCR4_TAR_0 ((uint32_t)0x00002000) /*!< Bit 0 */ #define FSMC_PCR4_TAR_1 ((uint32_t)0x00004000) /*!< Bit 1 */ #define FSMC_PCR4_TAR_2 ((uint32_t)0x00008000) /*!< Bit 2 */ #define FSMC_PCR4_TAR_3 ((uint32_t)0x00010000) /*!< Bit 3 */ #define FSMC_PCR4_ECCPS ((uint32_t)0x000E0000) /*!< ECCPS[2:0] bits (ECC page size) */ #define FSMC_PCR4_ECCPS_0 ((uint32_t)0x00020000) /*!< Bit 0 */ #define FSMC_PCR4_ECCPS_1 ((uint32_t)0x00040000) /*!< Bit 1 */ #define FSMC_PCR4_ECCPS_2 ((uint32_t)0x00080000) /*!< Bit 2 */ /****************** Bit definition for FSMC_PCR4 register *******************/ #define FSMC_PCR4_PWAITEN ((uint32_t)0x00000002) /*!< Wait feature enable bit */ #define FSMC_PCR4_PBKEN ((uint32_t)0x00000004) /*!< PC Card/NAND Flash memory bank enable bit */ #define FSMC_PCR4_PTYP ((uint32_t)0x00000008) /*!< Memory type */ #define FSMC_PCR4_PWID ((uint32_t)0x00000030) /*!< PWID[1:0] bits (NAND Flash databus width) */ #define FSMC_PCR4_PWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */ #define FSMC_PCR4_PWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */ #define FSMC_PCR4_ECCEN ((uint32_t)0x00000040) /*!< ECC computation logic enable bit */ #define FSMC_PCR4_TCLR ((uint32_t)0x00001E00) /*!< TCLR[3:0] bits (CLE to RE delay) */ #define FSMC_PCR4_TCLR_0 ((uint32_t)0x00000200) /*!< Bit 0 */ #define FSMC_PCR4_TCLR_1 ((uint32_t)0x00000400) /*!< Bit 1 */ #define FSMC_PCR4_TCLR_2 ((uint32_t)0x00000800) /*!< Bit 2 */ #define FSMC_PCR4_TCLR_3 ((uint32_t)0x00001000) /*!< Bit 3 */ #define FSMC_PCR4_TAR ((uint32_t)0x0001E000) /*!< TAR[3:0] bits (ALE to RE delay) */ #define FSMC_PCR4_TAR_0 ((uint32_t)0x00002000) /*!< Bit 0 */ #define FSMC_PCR4_TAR_1 ((uint32_t)0x00004000) /*!< Bit 1 */ #define FSMC_PCR4_TAR_2 ((uint32_t)0x00008000) /*!< Bit 2 */ #define FSMC_PCR4_TAR_3 ((uint32_t)0x00010000) /*!< Bit 3 */ #define FSMC_PCR4_ECCPS ((uint32_t)0x000E0000) /*!< ECCPS[2:0] bits (ECC page size) */ #define FSMC_PCR4_ECCPS_0 ((uint32_t)0x00020000) /*!< Bit 0 */ #define FSMC_PCR4_ECCPS_1 ((uint32_t)0x00040000) /*!< Bit 1 */ #define FSMC_PCR4_ECCPS_2 ((uint32_t)0x00080000) /*!< Bit 2 */ |
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8 个讨论
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坐等更新 欢迎连载 不过能不能多一些说明呢
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what??????
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