这个程序改了好久，班里同学都看过找不出问题啊

这是一个奇偶数控分频器的程序，我可以实现就分频了，可是K-OR占空比不是50%是怎么回事，谁能找出问题所在
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENtiTY DIV IS
   PORT (CLK:IN STD_LOGIC;
         D:in STD_LOGIC_VECTOR(3 DOWNTO 0);
          K_OR,K1,K2:OUT STD_LOGIC);
END;
ARCHITECTURE bhv OF DIV IS
   SIGNAL R,C1,C2:STD_LOGIC_VECTOR(3 DOWNTO 0);
   SIGNAL M1,M2:STD_LOGIC; --VARIABLE R: INTEGER RANGE 0 TO 1;
BEGIN
PROCESS(R) BEGIN
R<=D+1;
END PROCESS;
PROCESS(CLK,C1)   BEGIN
--R := (D REM 2);--TO_STDLOGICVECTOR(TO_BITVECTOR(R) SRL(1)))
   IF RISING_EDGE(CLK) THEN
IF (D(0)='1') THEN
  IF (C1=D-1) THEN C1<="0000";  ELSE C1<= C1+1;  END IF;
   IF (C1="0001") THEN M1<=NOT M1;  ELSIF (C1<="0"&R(3 DOWNTO 1)) THEN M1<=NOT M1;END IF;
   ELSE--IF(D(0)='0') THEN
   IF (C1=D-1) THEN C1<="0000";  ELSE C1<= C1+1;  END IF;
   IF (C1="0000") THEN M1<=NOT M1;  ELSIF (C1<="0"&D(3 DOWNTO 1))THEN M1<=NOT M1; END IF;
END IF; END IF;
END PROCESS;
PROCESS(CLK,C2)   BEGIN
   IF FALLING_EDGE(CLK) THEN
   IF (D(0)='1') THEN
  IF (C2=D-1) THEN C2<="0000";  ELSE C2<= C2+1;  END IF;
   IF (C2="0001") THEN M2<=NOT M2;  ELSIF (C2<="0"&R(3 DOWNTO 1))THEN M2<=NOT M2;END IF;
   --ELSIF(D(0)='0') THEN
   --IF (C2=D-1) THEN C2<="0000";  ELSE C2<= C2+1;  END IF;
   --IF (C2="0000") THEN M2<=NOT M2;  ELSIF (C2<=TO_STDLOGICVECTOR(TO_BITVECTOR(D) SRL(1))) THEN M2<=NOT M2; END IF;
END IF; END IF;
END PROCESS;
K1<=M1;  K2<=M2;  K_OR<=M1 OR M2;
END bhv;