求助 ：via not on a net 是什么意思啊

用Allegro做PCB时，放置器件时总是会出现DRC错误，里面
Detailed DRC ErrorsConstraint NameDRC Marker LocationRequired ValueActual ValueConstraint SourceConstraint Source TypeElement 1Element 2
Package to Package Spacing(406.1983 404.9753)0 MM0.45 MMNONEDESIGNFilled Rectangle "Package Geometry/Place_Bound_Top"Filled Rectangle "Package Geometry/Place_Bound_Top"
SMD Pin to Thru Via Spacing(402.0600 418.1772)0.127 MMOVERLAPDEFAULTNET SPACING CONSTRAINTSVia "Not On A Net, Via, (402.1753 418.4594)"Connect Pin "J3.1"
SMD Pin to Thru Via Spacing(406.9388 407.4617)0.127 MMOVERLAPDEFAULTNET SPACING CONSTRAINTSConnect Pin "J2.1"Via "Not On A Net, Via, (406.6482 407.5537)"
SMD Pin to Thru Via Spacing(406.8510 406.9799)0.127 MMOVERLAPDEFAULTNET SPACING CONSTRAINTSConnect Pin "J2.1"Via "Not On A Net, Via, (406.6058 406.7989)"
SMD Pin to Thru Via Spacing(406.0815 406.1334)0.127 MM0.1158 MMDEFAULTNET SPACING CONSTRAINTSConnect Pin "J2.2"Via "Not On A Net, Via, (405.8576 405.9266)"
SMD Pin to Thru Via Spacing(406.8923 406.6947)0.127 MMOVERLAPDEFAULTNET SPACING CONSTRAINTSConnect Pin "J2.2"Via "Not On A Net, Via, (406.6058 406.7989)"
SMD Pin to Thru Via Spacing(406.1520 405.8475)0.127 MMOVERLAPDEFAULTNET SPACING CONSTRAINTSConnect Pin "J2.3"Via "Not On A Net, Via, (405.8576 405.9266)"这个via not on a net是什么意思啊，明明是一个表贴的器件，也没有开始布线，怎么会有VIA，搞不懂，希望高手指点