求助 有好多错误 求指点

module clock (CLK,nRST,A,B,O1,O2,O3,O4);
input CLK,A,B,nRST;
output[3:0] O1,O2,O3,O4;
parameter TOP=9;
parameter[3:0] s0=4'b0000,s1=4'b0001,s2=4'b0010,s3=4'b0100,s4=4'b1000;
reg[3:0] CS,NS;
reg[3:0] O1,O2,O3,O4;
always@(posedge CLK,negedge nRST)begin
if(!nRST)cs<=s0;
else    CS<=NS;
end
always@(CS,A,B)begin
case(CS)
   s0:begin
   if(A&&B) NS=s1;
   end
   s1:begin
   if(A) NS=s1;
   if(B) NS=s2;
   end
   s2:begin
   if(A) NS=s2;
   if(B) NS=S3;
   end
   s3:begin
   if(A) NS=s3;
   if(B) NS=S4;
   end
   s4:begin
   if(A) NS=s4;
   if(B) NS=s0;
   end
   default:begin NS=s0;end
   endcase
   end
   always@(posedge CLK,negedge nRST,O1,O2,O3,O4)begin
    if(!nRST) begin O1<=4'b0000,O2<=4'b0000,O3<=4'b0000,O4<=4'b0000;end
    if(O2==4'b0110) begin O1<=4'b0000,O2<=4'b0000;end
    if(O3==4'b0100&&O4==4'b0010)begin O1<=4'b0000,O2<=4'b0000,O3<=4'b0000,O4<=4'b0000;end
else begin
case(NS)
s0:O1<=O1+4'b0001,O2<=O2+4'b0001,O3<=O3+4'b0001,O4<=O4+4'b0001 ;
s1:O1<=O1+4'b0001;
s2:O2<=O2+4'b0001;
s3:O3<=O3+4'b0001;
s4:O4<=O4+4'b0001;
default:begin O1<=4'b0000,O2<=4'b0000,O3<=4'b0000,O4<=4'b0000;end
endcase
end
end
endmodule

Error (10170): Verilog HDL syntax error at clock.v(37) near text ",";  expecting ";"
Error (10170): Verilog HDL syntax error at clock.v(38) near text ",";  expecting ";"
Error (10170): Verilog HDL syntax error at clock.v(39) near text ",";  expecting ";"
Error (10170): Verilog HDL syntax error at clock.v(42) near text ",";  expecting ";"
Error (10170): Verilog HDL syntax error at clock.v(42) near text ";";  expecting ":", or ","
Error (10170): Verilog HDL syntax error at clock.v(47) near text ",";  expecting ";"
Error (10112): Ignored design unit "clock" at clock.v(1) due to previous errors
Error: Quartus II Analysis & Synthesis was unsuccessful. 7 errors, 0 warnings
        Error: Peak virtual memory: 206 megabytes
        Error: Processing ended: Thu Dec 12 21:04:38 2013
        Error: Elapsed time: 00:00:01
        Error: Total CPU time (on all processors): 00:00:00
Error: Quartus II Full Compilation was unsuccessful. 9 errors, 0 warnings