发送程序: library ieee; useieee.std_logic_1164.all; port( clk,en:in std_logic; Send_data:in std_logic_vector(9 downto 0); serial:out std_logic); end correspond; architecturecorrespond_arc of correspond is begin process(clk) variable count:integer range 0 to 9 :=0; begin if (en='0') then count:=0; serial<='1'; elsif rising_edge(clk) then if (count=9) then serial<=Send_data(9); else serial<=Send_data(count); count:=count+1; end if; end if; end process; endcorrespond_arc;
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