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基于数字秒表设计 1.分频器代码: 将50MHz脉冲变成100Hzlibrary ieee; use ieee.std_logic_1164.all; entity div is port(clr,clk: in bit;q: buffer bit;q1:bufferbit); end div; architecture a of div is signal counter1:integer range 0to 24999; signal counter2:integer range 0to 4; begin process(clr,clk) begin if (clk='1' and clk'event)then if clr='0' then counter1<=0; elsif counter1=24999 then counter1<=0; q<= not q; else counter1<=counter1+1; end if; end if; end process; process(q) begin if(q'event and q='1') then if clr='0' then counter2<=0; elsif counter2=4 then counter2<=0; q1<=not q1; else counter2<=counter2+1; end if; end if; end process; end a; 2.十进制计数器代码: 原理为加法计数器,计数十时由cout进位 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity count10 is port(clr,start,clk: in bit; cout: out bit; daout: outstd_logic_vector(3 downto 0)); end count10; architecture a of count10 is signal temp:std_logic_vector(3downto 0); begin process(clk,clr) begin if clr='0' then temp<="0000"; cout<='0'; elsif (clk'event andclk='1') then if start='0' then if temp>="1001"then temp<="0000"; cout<='1'; else temp<=temp+1; cout<='0'; end if; end if; end if; daout<=temp; end process; end a; 3.六进制计数器代码: 原理为加法计数器,计数六时由cout进位。 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity c6 is port(clr,start,clk: in bit; daout: outstd_logic_vector(3 downto 0); cout: out std_logic); end c6; architecture a of c6 is signal temp:std_logic_vector(3downto 0); begin process(clk,clr) begin if clr='0' then temp<="0000"; cout<='0'; elsif (clk'event and clk='1')then if start='0' then if temp>="0101" then temp<="0000"; cout<='1'; else temp<=temp+1; cout<='0'; end if; end if; end if; end process; daout<=temp; end a; 4.数据选择和数码管选择模块代码: 其功能是选择个计数端口来的数据,当相应的数据到来时数据选择器选择器数据后输出给数码管,并由数码管显示。 library ieee; use ieee.std_logic_1164.all; USE ieee.std_logic_UNSIGNED.all; entity seltime is port(clr,clk: in bit; dain0,dain1,dain2,dain3,dain4,dain5: in std_logic_vector(3 downto 0); sel: out std_logic_vector(5downto 0); daout: outstd_logic_vector(3 downto 0)); end seltime; architecture a of seltime is signal temp:integer range 0 to 5; begin process(clk) begin if (clr='0') then daout<="0000"; sel<="000000"; temp<=0; elsif (clk='1'andclk'event) then if temp=5 thentemp<=0; else temp<=temp +1; end if; case temp is when0=>sel<="111110";daout<=dain0; when1=>sel<="111101";daout<=dain1; when2=>sel<="111011";daout<=dain2; when3=>sel<="110111";daout<=dain3; when4=>sel<="101111";daout<=dain4; when5=>sel<="011111";daout<=dain5; end case; end if; end process; end a; use ieee.std_logic_1164.all; entity deled is port(num:in std_logic_vector(3downto 0); led:out std_logic_vector(6downto 0)); end deled ; architecture a of deled is begin process(num) begin case num is when"0000"=>led<="1000000";-----------3FH when"0001"=>led<="1111001";-----------06H when"0010"=>led<="0100100";-----------5BH when"0011"=>led<="0110000";-----------4FH when"0100"=>led<="0011001";-----------66H when"0101"=>led<="0010010";-----------6DH when"0110"=>led<="0000010";-----------7DH when"0111"=>led<="1011000";-----------27H when"1000"=>led<="0000000";-----------7FH when"1001"=>led<="0010000";-----------6FH whenothers=>led<="1111111";-----------00H end case; end process; end a; |
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