library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity vhdl_verilog is
port(
clk:in std_logic;
pwm_in:in std_logic_vector(7 downto 0);
pwm_out:out std_logic
);
end vhdl_verilog;
architecture pwm of vhdl_verilog is
signal acc: std_logic_vector(8 downto 0);
begin
process(clk,pwm_in)
begin
if rising_edge(clk) then
acc<=acc(7 downto 0) + pwm_in ;
end if;
end process;
pwm_out<=acc(8);
end pwm;