通过FPGA对VGA的控制。。。。

module vgaexp3(clk50m,rst_n,r,g,b,vs,hs);
output r,g,b,vs,hs;
input clk50m,rst_n;
reg [10:0]count_hs,count_vs;
//reg vs,hs;
wire clk40m;
//-------------------------------------通过PLL输出 40MHz
pll_sec pll_sec_inst  (
.inclk0 ( clk50m ),
.c0 ( clk40m ),
);
//------------------------------------------ 产生 HS,VS
always @(posedge clk40m or negedge rst_n)
if(!rst_n)
count_hs <= 11'd0;
else if(count_hs == 11'd1056)
count_hs <= 11'd0;
else
count_hs <= count_hs + 1'b1;
always@(posedgeclk40m  or negedge rst_n)
if(!rst_n)
count_vs <= 11'd0;
else if(count_vs == 11'd628)
count_vs <= 11'd0;
else
if(count_hs == 11'd1056)count_vs <= count_vs + 1'b1;
/*always@(posedgeclk40m)
begin
if(count_hs <= 11'd128) hs <= 1'b0;
else hs <= 1'b1;
if(count_vs <= 11'd4) vs <= 1'b0;
else vs <= 1'b1;
end
*/
assign hs=(count_hs<=11'd128) ? 1'b0 : 1'b1;
assign vs=(count_vs<=11'd4) ? 1'b0 : 1'b1;
//----------------------------------------------------------有效区输出颜色
reg valid_r;
always@(posedgeclk40m or negedge rst_n )
if(!rst_n)
valid_r <= 1'b0;
else
if((count_hs>11'd216&&count_hs<11'd1017)&&(count_vs>11'd27&&count_vs<11'd627))
    valid_r<=1'b1;
else
  valid_r<=1'b0;
assign r = valid_r?1:0;
assign b = valid_r?1:0;
assign g = valid_r?0:0;
endmodule


这是源程序，根据原理来说没问题，为什么连到显示器上后显示没信号输入，为什么呢？求助。。。。