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library ieee;
use ieee.std_logic_arith.all; use ieee.std_logic_1164.all; entity filter is port( clk,reset :in std_logic; sample_in :in signed (7 downto 0); result_out :out signed(20 downto 0)); end filter; architecture behave of filter is type coef_arr is array(0 to 18) of signed (7 downto 0); constant coefs: coef_arr:=coef_arr'("10000101","00000100","10000101","10001001","10000001","00000000","10001111","10001101","00011000","00110000","00011000",10001101","10001111","00000000","10000001","10001001","10000101","00000100","10000101"); begin process(clk,reset) type shift_register is array (18 downto 0) of signed (7 downto 0); variable shift : shift_register; variable temp : signed(7 downto 0); variable mul_value :signed(15 downto 0); variable acc_value : signed (20 downto 0); begin if(reset='0')then for i in 0 to 17 loop shift(i):=(others=>'0'); end loop; result_out<=(others=>'0'); elsif (clk'event and clk='1')then temp:=sample_in; mul_value:=temp*coefs(0); acc_value:=conv_signed(mul_value,20); for i in 17 downto 0 loop mul_value:=shift(i)*coefs(i+1); acc_value:=acc_value+conv_signed(mul_value,20); shift(i+1):=shift(i); end loop; shift(0):=temp; result_out<=acc_value; end if; end process; end behave; |
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