[经验]

刚入门，虽写得一般。但下载到板子里顺利通过测试

2013-5-6 19:41:24

1709

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity qudong is
port (clk,ad: in std_logic;
   shA,SHB,SHC,Q11,Q12,Q13,Q21,Q22,Q23,rs,cp,sp: out std_logic);
end qudong;
architecture JIEGOU of qudong is
SIGNAL D:std_logic_vector( 1 to 4);
SIGNAL F1,F2,R,S:std_logic;
SIGNAL clkin,clks,clk1,clk2,clko,SH0,SH1,SH2:STD_LOGIC;
BEGIN
process(clk)
begin
if(clk'event and clk='1')then
clko<=not clko;
end if;
end process;
process(clko)
begin
if(clko'event and clko='1')then
clk1<=not clk1;
end if;
end process;
process(clk1)
begin
if(clk1'event and clk1='1')then
clk2<=not clk2;
end if;
end process;
PROCESS(CLK,ad)
begin
if(clk'event and clk='1')then
if (ad='0') then
clkin<=clk1;
  else
clkin<=clk2;
end if;
end if;
end process;
PROCESS(clkin)
variable q:integer :=0;
BEGIN
if(clkin'event and clkin='1')then
IF q = 12  THEN
clks <= NOT clks ;
q:=0;
ELSE q:=q+1;
END IF;
end if;
CASE q IS
WHEN 1=> R <= '1';
WHEN OTHERS=> R <= '0';
end case;
S <= SH2 and R;
F1 <= clks OR SH1 ;
F2 <= NOT F1 ;
end process;
PROCESS(clkin)
variable count:integer :=0;
begin
if(clkin'event and clkin='1')then
if (count < 33369) then
  if (count >=0 AND count <=48)then
SH2 <= '0';
  else
SH2 <='1';
  end if;
  if (count >= 0 AND count <= 10) OR( count > 34 AND count <47) then
  SH0 <='0';
  SH1 <='1';
elsif (count > 10 AND count <= 34) then
SH0 <= '1';
SH1 <= '1';
else
SH0 <='0';
SH1 <='0';
  end if;
count := count+1 ;
ELSE
count := 0 ;
END IF ;
end if;
end process;

PROCESS(R) --CP
BEGIN
if(clkin'event and clkin='1')then
D(2) <= S;
D(1) <= D(2);
END IF;
END PROCESS;
PROCESS(D(1))--SP
BEGIN
if(clkin'event and clkin='1')then
D(4) <= D(1);
D(3) <= D(4);
END IF;
END PROCESS;
SHA<= SH0;
SHB<= SH0;
SHC<= SH0;
Q11<=F1;
Q12<=F1;
Q13<=F1;
Q21<=F2;
Q22<=F2;
Q23<=F2;
sp<=S;
cp<=D(1);
rs<=D(3);
end JIEGOU;