程序

module johnson(clk,rst_n,led);
input clk;
input rst_n;
output[3:0]led;
parameter led_dir=1'b1;
parameter led_on=1'b0;
//********************************************
reg[23:0] cnt;
always@(posedge CLK or negedge rst_n)
begin
if(!rst_n) cnt<=24'b0;
else cnt <=cnt+1'b1;
end
//**********************************************
reg[3:0] led_r;
always@(posedge clk or negedge rst_n)
begin
if(!rst_n) led_r <=4'b0001;
      
else if(cnt==24'hffffff && led_on)
begin
      if(led_dir)led_r <=(led_r[2:0],led_r[3]);  
       else
      led_r <=(led_r[0],led_r[3:1]);         
      assign led=led_r;
end
      end
endmodule
    怎么总是有错误啊，求救！


Error (10170): Verilog HDL syntax error at johnson.v(25) near text ",";  expecting ")"
Error (10170): Verilog HDL syntax error at johnson.v(25) near text ")";  expecting "<=", or "="
Error (10170): Verilog HDL syntax error at johnson.v(27) near text ",";  expecting ")"
Error (10170): Verilog HDL syntax error at johnson.v(27) near text ")";  expecting "<=", or "="
Error (10112): Ignored design unit "johnson" at johnson.v(1) due to previous errors
Error: Quartus II Analysis & Synthesis was unsuccessful. 5 errors, 0 warnings
Error: Peak virtual memory: 169 megabytes
Error: Processing ended: Tue Apr 23 15:50:35 2013
Error: Elapsed time: 00:00:01
Error: Total CPU time (on all processors): 00:00:01
Error: Quartus II Full Compilation was unsuccessful. 7 errors, 0 warnings！