请大家帮忙，编译不通过，我这个代码是实现5G和2,4G串行.....

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity demo is

port(
5G_strobe: in std_logic ;
5G_data_in: in std_logic;
24G_strobe: in std_logic;
24G_data_in: in std_logic;        
5G_data_out:out std_logic_vector(23 downto 0);
        24G_data_out:out std_logic_vector(23 downto 0);
        24a: out std_logic;
24b: out std_logic;
24c: out std_logic;
24d: out std_logic;
24e: out std_logic;
24f: out std_logic;
24g: out std_logic;
24h: out std_logic;
        24i: out std_logic;
24j: out std_logic;
24k: out std_logic;
24l: out std_logic;
        5a: out std_logic;
5b: out std_logic;
5c: out std_logic;
5d: out std_logic;
5e: out std_logic;
5f: out std_logic;
5g: out std_logic;
5h: out std_logic;
        5i: out std_logic;
5j: out std_logic;
5k: out std_logic;
5l: out std_logic);

end;

architecture demo_ben of demo is
signal 5Gset: integer range 0 to 1;
signal 5Gcouter:integer range 0 to 23;
signal 24Gset: integer range 0 to 1;
signal 24Gcouter:integer range 0 to 23;
begin
5G_radio:process(5G_strobe)
begin
if rising_edge(5G_strobe) then
5G_data_out(23)<=5G_data_in;
5G_data_out(22 downto 0)<=5G_data_out(23 downto 1);
if 5Gcouter=23 then
5Gcouter<=0; 5Gset<=0;
else 5Gcouter<=5Gcouter+1;5Gset<= 1;
if 5Gset=0 then
5a<=5G_data_out(0);
5b<=5G_data_out(1);
5c<=5G_data_out(2);
5d<=5G_data_out(3);
5e<=5G_data_out(4);
5f<=5G_data_out(5);
5g<=5G_data_out(6);
5h<=5G_data_out(7);
5i<=5G_data_out(8);
5j<=5G_data_out(9);
5k<=5G_data_out(10);
5l<=5G_data_out(11);
end if;
end if;
end if;
end process 5G_radio;
24G_radio:process(24G_strobe)
begin
if rising_edge(24G_strobe) then
24G_data_out(23)<=24G_data_in;
24G_data_out(22 downto 0)<=24G_data_out(23 downto 1);
if 24Gcouter=23 then
24Gcouter<=0; 24Gset<=0;
else 24Gcouter<=24Gcouter+1;24Gset<= 1;
if 24Gset=0 then
24a<=24G_data_out(0);
24b<=24G_data_out(1);
24c<=24G_data_out(2);
24d<=24G_data_out(3);
24e<=24G_data_out(4);
24f<=24G_data_out(5);
24g<=24G_data_out(6);
24h<=24G_data_out(7);
24i<=24G_data_out(8);
24j<=24G_data_out(9);
24k<=24G_data_out(10);
24l<=24G_data_out(11);
end if;
end if;
end if;
end process 24G_radio;
end demo_ben;