新手求助

2009-3-16 12:47:09 3516

0 library ieee; use ieee.std_logic_1164.all ; use ieee.std_logic_unsigned.all ; entity li is port (clk ,j ,en ,d ,c ,b ,a :in std_logic ;r1 ,r2 :out std_logic) ; end ; architecture behave of li is signal cq ,k ,mo :std_logic_vector (16 downto 0) ; signal cao1 ,cao2 :std_logic ; signal instruction :std_logic_vector (3 downto 0) ; begin instruction <= d &c &b &a ; with instruction select mo <="00000000000000111"when"0001", "00000000000001111"when"0010", "00000000000011111"when"0011", "00000000000111111"when"0100", "00000000001111111"when"0101", "00000000011111111"when"0110", "00000000111111111"when"0111", "00000001111111111"when"1000", "00000011111111111"when"1001", "00000111111111111"when"1010", "00001111111111111"when"1011", "00011111111111111"when"1100", "00111111111111111"when"1101", "01111111111111111"when"1110", "11111111111111111"when"1111", "00000000000000111"when others ; process (clk ,en ,j ,k ,cq) begin if clk'event and clk = '1'then k <= mo ; if en = '1'then if j = '0'then if cq < k then cq <= cq + 1 ; else cq <= ( (others = > '0') ; end if ; else if cq > 0 then cq <= cq - 1 ; else cq <= k ; end if ; end if ; else cq <= ( (others = > '0') ; end if ; end if ; end process ; process (en ,j ,cq ,k) begin if en = '1'then if j = '0'then if cq = k then cao1 <= '1'; else cao1 <= '0'; end if ; cao2 <= '0'; else if cq ="00000000000000000"then cao2 <= '1'; else cao2 <= '0'; end if ; cao1 <= '0'; end if ; else cao1 <= '0';cao2 <= '0'; end if ; end process ; r1 <= cao1 ; r2 <= cao2 ; end behave ; 以上是网上参考的变模计数器的VHDL代码，然而我在使用MAX PLUS 2 编译时却显示： unexpected end of file try using the text editor's syntax coloring command to find the missing delimiter or key word 检查一上午仍然没找到错误的地方，望各位大侠指导 0
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