SMBus控制器 Xilinx提供VHDL代码
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Readme File for SMBus Customer Pack
Created: 1/11/01 JRH
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DISCLAIMER
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THIS DESIGN IS PROVIDED TO YOU 揂S IS? XILINX MAKES AND YOU RECEIVE NO WARRANtiES OR
CONDITIONS, EXPRESS, IMPLIED, STATUTORY OR OTHERWISE, AND XILINX SPECIFICALLY DISCLAIMS ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR A PARTICULAR
PURPOSE. This design has not been verified on hardware (as opposed to simulations), and it should be used only as an
example design, not as a fully functional core. XILINX does not warrant the performance, functionality, or operation of this
Design will meet your requirements, or that the operation of the Design will be uninterrupted or error free, or that defects in
the Design will be corrected. Furthermore, XILINX does not warrant or make any representations regarding use or the
results of the use of the Design in terms of correctness, accuracy, reliability or otherwise.
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File Contents
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This zip file contains the following folders:
work -- XST and ModelSim compiled VHDL files
-- VHDL Source Files:
smbus.vhd - top level file
smbus_control.vhd - control function for the SMBus master/slave
uc_interface.vhd - uC interface function for a Hitachi SH7750-like uC
shift.vhd - shift register
upcnt4.vhd - 4-bit up counter
upcnt9.vhd - 9-bit up counter
upcnt21.vhd - 21-bit up counter
smbus_timesim.vhd - XST compiled version of smbus.vhd, smbus_control.vhd,
and uc_interface.vhd which contains the timing
delay data for the XCR3256XL-7TQ144 device to
which this SMBus design was targeted.
--VHDL Testbench Files:
micro_test.vhd -- top-level VHDL testbench for simulation that
instantiates micro_tb.vhd, pullup.vhd, and smbus.vhd.
micro_tb.vhd -- VHDL simulation testbench that tests two
instantiations of the SMBus design. It configures
one as a master and one as a slave and then
the two SMBus designs transfer data over SMBus.
pullup.vhd -- models a pull-up resistor
-- ModelSim DO files:
micro_test.do -- functional simulation script file that compiles smbus.vhd,
smbus_control.vhd, uc_interface.vhd, shift.vhd,
upcnt4.vhd, upcnt9.vhd, ucnt21.vhd, micro_test.vhd,
micro_tb.vhd, and pullup.vhd. Then loads the design
micro_test and calls wave.do
wave.do -- configures wave window for functional simulation
micro_test_post.do -- post-route simulation script file that compiles time_sim.vhd,
micro_test_post.vhd, micro_tb.vhd, and pullup.vhd. Then
loads the design micro_test_post and calls wave_post.do
wave_post.do -- configures wave window for post-route simulation
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Design Notes
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The SMBus design was designed using the timing diagrams in Section 23.3.3 - BUS TIMING of the specification for
the Hitachi SH7750 uC. Complete documentation for the design can be found in XAPP353 available for download from
the Xilinx website.
All of the register addresses are defined as constants in the VHDL source files and can be easily customized for customer
use. The MBASE address is defined as a generic and can also be easily changed and customized for customer use. In
addition, this design outputs the MCF signal on a pin which can be used by the uC as a quick indication that the SMBus
transfer is complete.
This design is targeted to the XCR3256XL-7TQ144C CoolRunner CPLD. This is a 3V, 256 macrocell device in a 144TQFP
package. The fitter was allowed to pick the pin-out for the device.
IMPORTANT NOTE: This design uses the SMBus SCL signal as a clock. This requires that the SCL signal have clean, fast
edges on both the rising and falling edges of this signal. Slow rise and fall times on this signal can show noise effects
which can cause improper clocking of registers within the CoolRunner CPLD. If the loading of the SCL signal in the system
is such that the rise and fall times are slow (>100nS), this signal will need to be buffered external to the CPLD.
Please also note that this design has been verified through simulations, but not on actual hardware.
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