LCD 控制程序(计数器)

2012-8-12 12:27:32 2989

0 LCD 控制程序(计数器).rar (3.4 KB, 下载次数: 2 ) LCD 控制程序(计数器) JTAG下载线驱动程序及方法.rar (493.22 KB, 下载次数: 2 ) ISPl362在基于FPGA的红外成像系统中的应用.rar (212.75 KB, 下载次数: 1 ) IP核生成文件：XilinxAltera.pdf (374.23 KB, 下载次数: 1 ) library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity counter is Port ( clk : in std_logic; resetn : in std_logic; dout : out std_logic_vector(7 downto 0); lcd_en : out std_logic; lcd_rs : out std_logic; lcd_rw : out std_logic); end counter; architecture Behavioral of counter is component counter60 is Port ( clk : in std_logic; resetn : in std_logic; dout : out std_logic_vector(7 downto 0)); end component; component decoder is Port (din:in std_logic_vector(3 downto 0 ); dout:out std_logic_vector(8 downto 0) ); end component; component lcd_interface is port ( clk : in std_logic; resetn : in std_logic; dout_s10 : in std_logic_vector (8 downto 0); dout_s1 : in std_logic_vector (8 downto 0); lcd_data : out std_logic_vector (7 downto 0); lcd_en : out std_logic; lcd_rs : out std_logic; lcd_rw : out std_logic ); end component; signal ddout_s10 : std_logic_vector (8 downto 0); signal ddout_s1 : std_logic_vector (8 downto 0); signal ddout : std_logic_vector (7downto 0); begin u1: counter60 port map(clk,resetn,ddout); u2: decoder port map(ddout(7 downto 4),ddout_s10); u3: decoder port map(ddout(3 downto 0),ddout_s1); u4: lcd_interface port map(clk,resetn, ddout_s10,ddout_s1,dout,lcd_en, lcd_rs , lcd_rw); end Behavioral; -------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 13:36:10 03/30/06 -- Design Name: -- Module Name: count60 - Behavioral -- Project Name: -- Target Device: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity counter60 is Port ( clk : in std_logic; resetn : in std_logic; dout : out std_logic_vector(7 downto 0)); end counter60; architecture Behavioral of counter60 is signal count : std_logic_vector(7 downto 0); signal count_div : std_logic_vector (25 downto 0); begin dout <= count; process (clk) begin if (clk'event and clk = '1') then if (resetn = '0') then count_div <= (others => '0'); else if (count_div (25) = '1') then count_div <= (others =>'0') ; else count_div <= count_div + 1; end if; end if; end if; end process; process(clk ,resetn) begin if resetn= '0' then count <= (others => '0'); elsif rising_edge(clk) then if (count_div (25) = '1') then if count(3 downto 0)="1001" then count(3 downto 0)<="0000"; count(7 downto 4)<=count(7 downto 4) +1; else count(3 downto 0)<=count(3 downto 0)+1; end if; if count="01011001" then count<="00000000"; end if; end if; end if; end process; end Behavioral; -------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 13:25:37 03/30/06 -- Design Name: -- Module Name: decoder - Behavioral -- Project Name: -- Target Device: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity decoder is Port (din:in std_logic_vector(3 downto 0 ); --四位二进制码输入 dout:out std_logic_vector(8 downto 0) ); --输出LED七段码 end decoder; architecture Behavioral of decoder is begin process(din) begin case din is when "0000" => dout<="100110000";--30 when "0001" => dout<="100110001";--31 when "0010" => dout<="100110010";--32 when "0011" => dout<="100110011";--33 when "0100" => dout<="100110100"; --34 when "0101" => dout<="100110101";--35 when "0110" => dout<="100110110";--36 when "0111" => dout<="100110111";--37 when "1000" => dout<="100111000";--38 when "1001" => dout<="100111001";--39 when others => dout<="100100000" ; end case; end process; end Behavioral; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity lcd_interface is port ( clk : in std_logic; resetn : in std_logic; dout_s10 : in std_logic_vector (8 downto 0); dout_s1 : in std_logic_vector (8 downto 0); lcd_data : out std_logic_vector (7 downto 0); lcd_en : out std_logic; lcd_rs : out std_logic; lcd_rw : out std_logic ); end lcd_interface; architecture lcd_interface_arch of lcd_interface is signal lcd_we_n : std_logic; signal lcd_en_int : std_logic; signal w_comp_n : std_logic; signal seq_count : std_logic_vector (5 downto 0); signal lcd_rs_data : std_logic_vector (8 downto 0); signal delay_count : std_logic_vector (15 downto 0); signal lcd_addr : std_logic_vector (5 downto 0); type state_lcd_write_type is (lcd_write_idle, lcd_write_1, lcd_write_2, lcd_write_3, lcd_write_4); signal state_lcd_write : state_lcd_write_type; type state_type is (idle, wait_1, wait_2, state_1, state_2, state_3, done); signal state : state_type; begin -- The following state machine initializes the LCD and writes the following message -- to the LCD panel -- Memec Design -- MB1000 Board -- -- -- The LCD initialization sequence consist of writing the 0x38, 0x38, 0x06, 0x0e, -- 0x01, 0x80, 0xc0 sequence of hex numbers to the LCD control registers (please -- refer to the LCD datasheet for an explanation of the initialization sequence). -- At the end of the LCD initialization sequence, the LCD is ready to be written -- to starting with line 1. It should be noted that delays are inserted between -- 2 writes to the LCD panel to meet the LCD initialization requirements. Although, -- the LCD panel requires different delays between 2 writes, a fix delay of 20ms is -- inserted between 2 writes to simply the initialization design (the 20ms is the -- longest delay that is required by the LCD panel). A 22-bit counter is used to -- generate this fix delay. sequencer_state_register: process (clk, resetn) begin if (resetn = '0') then state <= idle; elsif (clk'event and clk = '1') then case state is when idle=> if (delay_count(15) = '1') then state <= wait_1; else state <= idle; end if; when wait_1=> if (delay_count(15) = '1') then state <= state_1; else state <= wait_1; end if; when state_1=> state <= state_2; when state_2=> if ((w_comp_n = '0') and (lcd_addr = "000110")) then state <= wait_2; elsif (w_comp_n = '0') then state <= wait_1; else state <= state_2; end if; -- The following sections performs the writing of the above message to the LCD -- panel. Similar to the initialization section, a fix delay is inserted between -- 2 LCD writes. The 22-bit counter used in the initialization section is also -- used here to generate the fix delay. when wait_2=> if (delay_count(15) = '1') then state <= state_3; else state <= wait_2; end if; when state_3=> if ((w_comp_n = '0') and (lcd_addr = "100111")) then state <= done; elsif (w_comp_n = '0') then state <= wait_2; else state <= state_3; end if; when done=> state <= done; end case; end if; end process sequencer_state_register; -- The following section generates a write enable (lcd_we_n) signal based on the -- state of the above state machine that is used to generate the lcd_en signal. sequencer_state_logic: process (state) begin case state is when idle=> lcd_we_n <= '1'; when wait_1=> lcd_we_n <= '1'; when wait_2=> lcd_we_n <= '1'; when state_1=> lcd_we_n <= '0'; when state_2=> lcd_we_n <= '0'; when state_3=> lcd_we_n <= '0'; when done=> lcd_we_n <= '1'; end case; end process sequencer_state_logic; -- The following sections uses the lcd_we_n signal to generate the lcd_en signal and -- a write complete signal (w_comp_n). The w_comp_n signal is used to reset various -- counters that are used to generate LCD control signals. state_lcd_write_register: process (clk, resetn) begin if (resetn = '0') then state_lcd_write <= lcd_write_idle; elsif (clk'event and clk = '1') then case state_lcd_write is when lcd_write_idle=> if (lcd_we_n = '0') then state_lcd_write <= lcd_write_1; else state_lcd_write <= lcd_write_idle; end if; when lcd_write_1=> if (seq_count = "000101") then state_lcd_write <= lcd_write_2; else state_lcd_write <= lcd_write_1; end if; when lcd_write_2=> if (seq_count = "011110") then state_lcd_write <= lcd_write_3; else state_lcd_write <= lcd_write_2; end if; when lcd_write_3=> if (seq_count = "110010") then state_lcd_write <= lcd_write_4; else state_lcd_write <= lcd_write_3; end if; when lcd_write_4=> state_lcd_write <= lcd_write_idle; end case; end if; end process state_lcd_write_register; state_lcd_write_logic: process (state_lcd_write) begin case state_lcd_write is when lcd_write_idle=> lcd_en_int <= '0'; w_comp_n <= '1'; when lcd_write_1=> lcd_en_int <= '0'; w_comp_n <= '1'; when lcd_write_2=> lcd_en_int <= '1'; w_comp_n <= '1'; when lcd_write_3=> lcd_en_int <= '0'; w_comp_n <= '1'; when lcd_write_4=> lcd_en_int <= '0'; w_comp_n <= '0'; end case; end process state_lcd_write_logic; -- The following process provides the LCD initialization data and also the ASCII -- characters needed to write the "Memec Design MB1000 Board" to the LCD panel. Once, -- the "Memec Design" is written to the first line of the LCD, hex 0xc0 is written to -- the LCD control register to start at line 2 and write the "MB1000 Board" to the -- LCD panel. The lcd_rs_data consist of the lcd_rs signal (MSB) and 8 bits of data -- (lcd_data). process (lcd_addr) begin case lcd_addr is when "000000" => lcd_rs_data <= "000111000"; -- lcd initializations when "000001" => lcd_rs_data <= "000111000"; when "000010" => lcd_rs_data <= "000000110"; when "000011" => lcd_rs_data <= "000001110"; when "000100" => lcd_rs_data <= "000000001"; when "000101" => lcd_rs_data <= "010000000"; when "000110" => lcd_rs_data <= "000001100"; when "000111" => lcd_rs_data <= "100100000"; when "001000" => lcd_rs_data <= "100100000"; when "001001" => lcd_rs_data <= dout_s10; -- lcd first line, "Memec Design" when "001010" => lcd_rs_data <= dout_s1; when "001011" => lcd_rs_data <= "100100000"; when "001100" => lcd_rs_data <= "100100000"; when "001101" => lcd_rs_data <= "100100000"; when "001110" => lcd_rs_data <= "100100000"; when "001111" => lcd_rs_data <= "100100000"; when "010000" => lcd_rs_data <= "100100000"; when "010001" => lcd_rs_data <= "100100000"; when "010010" => lcd_rs_data <= "100100000"; when "010011" => lcd_rs_data <= "100100000"; when others => lcd_rs_data <= "100100000"; end case; end process; -- The following is a 22-bit free running counter that is cleared when the reset -- signal is asserted or the MSB of the counter goes to 1. This counter is used -- to generate delays between back-to-back writes to the LCD panel during the -- initialization and also normal write cycles. process (clk) begin if (clk'event and clk = '1') then if (resetn = '0') then delay_count <= (others => '0'); else if (delay_count(15) = '1') then delay_count <= (others =>'0') ; else delay_count <= delay_count + 1; end if; end if; end if; end process; -- The following counter is used by the sequencer to generate the lcd_en signal. -- The counter is reset at the end of each write to the LCD when the w_comp_n -- signal goes active. process (clk) begin if (clk'event and clk = '1') then if ((resetn = '0') or (w_comp_n = '0')) then seq_count <= (others => '0'); elsif (lcd_we_n = '0') then seq_count <= seq_count + 1; end if; end if; end process; -- The following block generates the address pointer to the LCD initialization and -- data values. The counter is incremented at the end of each write to the LCD panel -- when the w_comp_n signal goes active. process (clk) begin if (clk'event and clk = '1') then if (resetn = '0') then lcd_addr <= (others => '0'); elsif (w_comp_n = '0') then if (lcd_addr = "011111") then lcd_addr <= "000000"; else lcd_addr <= lcd_addr + 1; end if; end if; end if; end process; -- The following sections define the LCD data and control signals. For this reference -- design, the lcd_rw signal is set to "0" forcing all LCD accesses to be write cycles. lcd_data <= lcd_rs_data(7 downto 0); lcd_en <= lcd_en_int; lcd_rs <= lcd_rs_data(8); lcd_rw <= '0'; end lcd_interface_arch; 0
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