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8位移位相加乘法器

杨磊

2012-8-10 17:57:31

3572

8位移位相加乘法器.doc (137 KB, 下载次数: 2 )

8位移位相加乘法器

8位加法器

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity adder8b is

port(cin:in std_logic;

a,b:in std_logic_vector(7 downto 0);

s:out std_logic_vector(7 downto 0);

cout:out std_logic);

end adder8b;

architecture behav of adder8b is

signal sint,aa,bb:std_logic_vector(8 downto 0);

begin

aa<='0'&a;

bb<='0'&b;

sint<=aa+bb+cin;

s<=sint(7 downto 0);

cout<=sint(8);

end behav;

一位乘法器

library ieee;

use ieee.std_logic_1164.all;

entity andarith is

port(abin:in std_logic;

din:in std_logic_vector(7 downto 0);

dout:out std_logic_vector(7 downto 0));

end andarith;

architecture behav of andarith is

begin

process(abin,din)

begin

for i in 0 to 7 loop

dout(i)<=din(i) and abin;

end loop;

end process;

end behav;

16位锁存器、右移寄存器

library ieee;

use ieee.std_logic_1164.all;

entity reg16b is

port(clk,clr:in std_logic;

d:in std_logic_vector(8 downto 0);

q:out std_logic_vector(15 downto 0));

end reg16b;

architecture behav of reg16b is

signal r16s:std_logic_vector(15 downto 0);

begin

process(clk,clr) begin

if clr='1' then

r16s<="0000000000000000";

elsif clk'event and clk='1' then

r16s(6 downto 0)<=r16s(7 downto 1);

r16s(15 downto 7)<=d;

end if;

end process;

q<=r16s;

end behav;

8位右移寄存器

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity sreg8b is

port(clk,load:in std_logic;

din:in std_logic_vector(7 downto 0);

qb:out std_logic);

end sreg8b;

architecture behav of sreg8b is

signal reg8:std_logic_vector(7 downto 0);

begin

process(clk,load)

begin

if clk'event and clk='1' then

if load='1' then

reg8<=din;

else

reg8(6 downto 0)<=reg8(7 downto 1);

end if;

end process;

qb<=reg8(0);

end behav;

通过以上程序产生各自封装构成的8位移位相加乘法器

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