ESP I/O寄存器的访问速度异常缓慢是怎么回事？

我注意到访问 ESP 的 I/O 寄存器时有一种奇怪的行为 - 尤其是 SPI FIFO 注册器SPI_W0。15.

I need to fill the FIFO as fast as possible so I ended up using "pure" asm to squeeze the max out of it. I'm using a "plain" RAM to FIFO copy, and the CCOUNT register to count the cycles needed to complete the action.
Here is the "main" code snippet (tmr hold the cycles count at the end):

        uint32 spiFIFO[16];

   asm volatile (
      "l32i.n %0, %2, 0   rn"                                    // this is here to preload the registers with correct address so to count only cycles needed to actually transfer data from RAM to FIFO
      "l32i.n %0, %3, 0   rn"
      "rsr.ccount %1      rn"
      "l32i.n %0, %2, 0   rn"                               // this line and
      "s32i.n %0, %3, 0   rn"                               // this one are a "move pair", moving one DWORD from RAM to FIFO
      "l32i.n %0, %2, 4   rn"
      "s32i.n %0, %3, 4   rn"
      "l32i.n %0, %2, 8   rn"
      "s32i.n %0, %3, 8   rn"
      "l32i.n %0, %2, 12   rn"
      "s32i.n %0, %3, 12   rn"
                ...                                                                  // "pairs" are repeated for various tests
      "rsr.ccount %0      rn"
      "sub %1, %0, %1      rn"
             : "=&r"(data),"=&r"(tmr):"r"(spiFIFO),"r"(SPI_W0(ESP_SPI_HSPI)));



所以，这是一件奇怪的事情：

5 对 = 11 个周期 （10 L32I/S32i RSR），看起来很棒
8 对 = 17 个周期再次很棒
10 对 = 28 个周期减速 - 1.4 cy/inst
12 对 = 51 个周期
16 对 = 64 个周期- 慢了2倍？！

为什么？？或者更好 - 如何避免这种情况？
It seems like some sort of "cache overrun" but the statement "ESP has no caches" is everywhere in the forum(s)...

读数 the FIFO register (or GPIO) is "constantly slow" - 12 cycles for a single l32i read instruction

有什么提示吗？