全面内容的数字跑表（含各个分频模块）

//____________________顶层模块
module piaobiaoa(clk,clr,pause, seg_out,sw);
input clk,clr,pause;
output [6:0] seg_out; //段选信号
output [2:0] sw; //位选信号
wire isstop; //标识秒表当前是否处于停止状态
wire zero;
wire clk100;
wire cout;
wire[6:0]cntVal0;
wire[5:0]cntVal1,cntVal2;
wire[3:0]sec_ten0,sec_ten1,sec_ten2;//高位
wire[3:0]sec_ge0,sec_ge1,sec_ge2;//低位
wire cout1,cout2;
//--------------------------------------------------
//以下为对各个子模块的调用
switch switchstop(clk,pause,isstop);
switch switchzero(clk,clr,zero);
div_10 a(clk,clk100);
count100 b(clk100,zero,isstop,cntVal0,cout);
count60 c(cout,zero,isstop,cntVal1,cout1);
count60 d(cout1,zero,isstop,cntVal2,cout2);
hexbcd f(cntVal0,sec_ten0,sec_ge0);
hexbcd g(cntVal1,sec_ten1,sec_ge1);
hexbcd h(cntVal2,sec_ten2,sec_ge2);
dis_sm e(clk100,sec_ten0,sec_ge0,sec_ten1,sec_ge1,sec_ten2,sec_ge2,seg_out,sw);
endmodule
//____________________
//_____________________分频模块
module div_ten(clk,clk100);//实现1kHZ转换为100HZ的十分频
input clk;
output reg clk100;
always @(posedge clk )
begin
clk100<=clk100+1;
if(clk100<=4)
begin clk100<=1;clk100=~clk100;end
else if(clk100==9)clk100<=0;
end
endmodule
//_______________
//_______以下为开关防抖动
module switch(clk,keyin,keyout);
parameter COUNTWIDTH=8;
input clk,keyin;
output reg keyout;
reg[COUNTWIDTH-1:0] counter;
wire clk_use;
assign clk_use=counter[COUNTWIDTH-1];
always@(posedge clk)
counter<=counter+1'b1;
always@(posedge clk_use)
keyout<=keyin;
endmodule
module switch(clk,keyin,keyout);
parameter COUNTWIDTH=8;
input clk,keyin;
output reg keyout;
reg[COUNTWIDTH-1:0] counter;
wire clk_use;
assign clk_use=counter[COUNTWIDTH-1];
always@(posedge clk)
counter<=counter+1'b1;
always@(posedge clk_use)
keyout<=keyin;
endmodule

//___________________
//___________以下为60计数
module count60(clk,clr,pause,cntVal,cout);
input clk,clr,pause;
output reg cout;
output reg[5:0] cntVal;
always @(posedge clk or posedge clr )
begin
if (clr==1) cntVal=0;
else if (!pause)
begin
if (cntVal>=59) begin cntVal=0; cout=1 ; end
else begin cntVal=cntVal+1; cout=0; end
end
end
endmodule


//__________________
//__________以下为100计数模块
module count100(clk,clr,pause,cntVal,clkout);
input clk,clr,pause;//
output reg clkout;//
output reg[6:0] cntVal;//
always@(posedge clk orposedge clr)
begin
if(clr) cntVal=0;
else if(!pause)
begin
cntVal = cntVal+1;
clkout =0;
if (cntVal>=99) begin cntVal=0; clkout =1; end
end
end
endmodule
//__________________
//___________以下为十六进制转换为十进制模块
module hexbcd(hexdata,shiwei,gewei);
input [6:0] hexdata;
output shiwei,gewei;
reg [3:0] shiwei,gewei;
always @(hexdata)
begin
shiwei=(hexdata/10);
gewei=(hexdata%10);
end
endmodule

//————————————————————
//__________以下为动态扫描模块
//输出段码
//输出位码
module dis_sm(clk,sec_ten0,sec_ge0, sec_ten1,sec_ge1,sec_ten2,sec_ge2,seg_out,sw);
input clk;
input [3:0] sec_ten0, sec_ten1, sec_ten2;//高位
input [3:0] sec_ge0,sec_ge1, sec_ge2;//低位
output reg[6:0] seg_out; //段选信号
output reg[2:0] sw; //位选信号
reg[6:0]sw_r;
//----------------------------------------------------------
always@(posedge clk)
begin
sw<=sw+1'b1;
if(sw>=6)sw<=0;
case(sw) //位信号输出
3'b000:sw_r<=sec_ge0;
3'b001:sw_r<=sec_ten0;
3'b010:sw_r<=sec_ge1;
3'b011:sw_r<=sec_ten1;
3'b100:sw_r<=sec_ge2;
3'b101:sw_r<=sec_ten2;
default:sw_r<=sec_ge0;
endcase
end
always@(*) //使用通配符
begin
case(sw_r) //用case语句进行译码
4'd0:{seg_out}<=7'b1111110;//显示0
4'd1:{seg_out}<=7'b0110000;//显示1
4'd2:{seg_out}<=7'b1101101;//显示2
4'd3:{seg_out}<=7'b1111001;//显示3
4'd4:{seg_out}<=7'b0110011;//显示4
4'd5:{seg_out}<=7'b1011011;//显示5
4'd6:{seg_out}<=7'b1011111;//显示6
4'd7:{seg_out}<=7'b1110000;//显示7
4'd8:{seg_out}<=7'b1111011;//显示8
4'd9:{seg_out}<=7'b1111110;//显示9
default: {seg_out}<=7'b1111110;//其他均显示0
endcase
end
endmodule