求助: VHDL编程，简单计数器modelsim

VHDL入门小白，在大学实验室做研究型实习。大项目是设计一个RISC-V架构的处理器。但是现在卡在老师布置的一个作业上。

老师推荐的设计框架是这样的。我一开始没看明白就直接创建一个实体，定义接口，然后在process里把计数器全部写完了。

-- Simple counter
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE ieee.numeric_std.ALL;
ENTITY simple_counter IS
	GENERIC(
		MAX_COUNT : integer :=5
);
	PORT(
		rst: IN std_logic := '1';
		clk: IN std_logic;
		mcount: OUT std_logic :='0';
		count: OUT integer range 0 to MAX_COUNT
);
END ENTITY simple_counter;

ARCHITECTURE Behavioral OF simple_counter IS
	SIGNAL count_up : std_logic_vector(3 downto 0);
BEGIN

PROCESS(clk)
VARIABLE tmp : integer;
BEGIN
	
	IF(rising_edge(clk)) THEN
		IF(rst='0') THEN
			count_up <=x"0";
--			mcount <= '0';
--		ELSIF(tmp > MAX_COUNT) THEN
--			count_up <= std_logic_vector(unsigned(MAX_COUNT));
--			mcount <= '1';
		ELSE 
			count_up <= count_up + x"1";
--			mcount <= '0';
		END IF;
	
	tmp := to_integer(unsigned(count_up));
	IF (tmp > MAX_COUNT) THEN
		count <= MAX_COUNT;
		mcount <= '1';
	ELSE 
		count <= tmp;
		mcount <='0';
	END IF;
	END IF;
END PROCESS;

END ARCHITECTURE;

但是在进行模拟的时候发现，无法完成老师的这一项模拟：

Test 4 Map therstport of the counter with theopenkeyword, and set theTB_MAX_COUNT constant of the testbench to the value 10. In this test the counter must be counting at all rising edges ofclk, irrespective of therstvalue.

我感觉testbench是没有问题的，问题应该还是在源代码上。思路我大概知道，创建3个component，定义内部接口的属性和信号，作3个port map。但是到了process这一步我又不明白了：是需要分别给3个component写各自的process吗？我在网上找到不少计数器的示例，但是没有找到分成3个block的计数器。

在此谢过各位。

-- Simple counter test bench
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY simple_counter_tb IS
END ENTITY simple_counter_tb;

ARCHITECTURE behavior OF simple_counter_tb IS 

CONSTANT TB_MAX_COUNT : integer := 10;
COMPONENT simple_counter
	GENERIC(
		MAX_COUNT : integer :=TB_MAX_COUNT
);
	PORT(
		rst: IN std_logic := '1';
		clk: IN std_logic;
		mcount: OUT std_logic;
		count: OUT integer range 0 to TB_MAX_COUNT
);

END COMPONENT simple_counter;
	--INPUTS
	signal rst : std_logic := '1';
	signal clk : std_logic;
	--OUTPUTS
	signal mcount: std_logic;
	signal count: integer range 0 to TB_MAX_COUNT;

BEGIN
	-- Instantiate the Design Under Test (DUT) and map its ports
	dut: simple_counter
	PORT MAP (
		-- Mapping: component port (left) => this arch signal/port (right)
		rst  => open,
		clk => clk,
		mcount => mcount,
		count => count 
	);
clock_proc:PROCESS
BEGIN
	clk <= '0';
	WAIT FOR 10 ns;
 	clk <= '1';
	WAIT FOR 10 ns;
END PROCESS;

stimuli:PROCESS
BEGIN
	rst <= '0';
	for i in 1 to 3 loop
		wait until rising_edge(clk);
	end loop;
	WAIT FOR 2 ns;
	
	rst <= '1';
	for i in 1 to TB_MAX_COUNT+1 loop
		wait until rising_edge(clk);
	end loop;
	WAIT FOR 2 ns;

	rst <= '0';
	for i in 1 to 3 loop
		wait until rising_edge(clk);
	end loop;
	WAIT FOR 2 ns;

	rst <= '1';
	for i in 1 to 3 loop
		wait until rising_edge(clk);
	end loop;
	WAIT FOR 2 ns;

	ASSERT false
	  REPORT "Simulation ended ( not a failure actually ) "
	  SEVERITY failure ;
	WAIT FOR 10ns;
END PROCESS;





END ARCHITECTURE;

*附件：lab-assign-s6-simple_counter.pdf