[经验]

SystemVerilog学习二 —— 分频器

鼻子抽筋

2012-3-7 09:52:40

3902 分频器

本帖最后由鼻子抽筋于 2012-3-7 09:53 编辑

1、divide-by-2 counter

**************************************************************

module clk_div (
input  wire  clk_in,
input  wire  enable,
input  wire  reset,
output reg clk_out
);
//--------------Code Starts Here-----------------------
always_ff @ (posedge clk_in)
if (reset) begin
  clk_out <= 1'b0;
end else if (enable) begin
  clk_out <= !clk_out ;
end

endmodule

*********************************************************************

RTL Viewer

2、divide-by-3 counter

***********************************************************************

module divide_by_3 (
input wire clk_in    , //Input Clock
input wire reset       , // Reset Input
output  wire clk_out       // Output Clock
);
//------------Internal Variables--------
reg [1:0] pos_cnt;
reg [1:0] neg_cnt;
//-------------Code Start-----------------
// Posedge counter
always_ff @ (posedge clk_in)
if (reset) begin
  pos_cnt <= 0;
end else begin
  pos_cnt <= (pos_cnt == 2'd2) ? 2'd0 : pos_cnt + 2'd1;
end
// Neg edge counter
always_ff @ (negedge clk_in)
if (reset) begin
  neg_cnt <= 0;
end else begin
  neg_cnt <= (neg_cnt == 2'd2) ? 2'd0 : neg_cnt + 2'd1;
end

assign clk_out = ((pos_cnt != 2'd2) && (neg_cnt != 2'd2));

endmodule

************************************************************************

RTL Viewer

3、divide-by-4.5 counter

***********************************************************************

module clk_div_45 (
input  wire clk_in, // Input Clock
input  wire enable, // Enable is sync with falling edge of clk_in
output reg  clk_out // Output Clock
);
//--------------Internal Registers----------------------
reg [3:0] counter1 ;
reg [3:0] counter2 ;
reg       clk_out1 ;
reg       clk_out2 ;

//--------------Code Starts Here-----------------------
always_ff @ (posedge clk_in or negedge enable)
if (enable == 1'b0) begin
counter1 <= 4'b0;
end else if (counter1 == 4'b1000)  begin
counter1 <= 4'b0;
end else begin
counter1 ++ ;
end

always_ff @ (posedge clk_in or negedge enable)
if (enable == 1'b0) begin
  counter2 <= 4'b0;
end else if (counter2 == 4'b1000)  begin
  counter2 <= 4'b0;
end  else begin
  counter2 ++ ;
end

always_ff @ (posedge clk_in or negedge enable)
if (enable == 1'b0)  begin
   clk_out1 <= 1'b0;
end else if (counter1 <= 4'b0010)  begin
   clk_out1<= 1'b1;
end else clk_out1<= 1'b0;

always_ff @ (posedge clk_in or negedge enable)
if (enable == 1'b0) begin
clk_out2 <= 1'b0;
end else if ((counter2 >= 4'b0110)&&(counter2 < 4'b1000)) begin
clk_out2 <= 1'b1;
end else clk_out2 <= 1'b0;

always_comb
begin
clk_out = clk_out1 | clk_out2;
end

endmodule

****************************************************************

RTL Viewer

Testbench

*******************************************************************************

`timescale 10 ns/ 10 ns
module clk_div_45_tb();
reg clk_in;
reg enable;
wire clk_out;
clk_div_45 i1 (
.clk_in(clk_in),
.clk_out(clk_out),
.enable(enable)
);
initial
begin
clk_in=0;
enable=0;
#1 enable =1;
end
always #1 clk_in = !clk_in;
endmodule
*******************************************************************************************