Virtex-6 Device
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User I/O Pins
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Virtex-6 FPGA Package
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FF1156
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FF1759
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XC6VLX240T
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Available User I/Os
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600
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720
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300
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360
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XC6VSX315T
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Available User I/Os
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600
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720
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Differential I/O Pairs
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300
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360
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2 各功能块特点
1
1
2
2.1 DSP48E1
Each DSP48E1slice fundamentally consists of a dedicated 25 × 18 bit two's complementmultiplier and a 48-bit accumulator, both capable of operating at 600 MHz.
2.2 Transceivers
Ø GTX
Each GTX transceiver is acombined transmitter and receiver capable of operating at a data rate between480 Mb/s and 6.6 Gb/s.
The GTX transmitter isfundamentally a parallel-to-serial converter with a conversion ratio of 8, 10,16, 20, 32, or 40.
Ø GTH
Each GTH transceiver is a combined transmitter andreceiver capable of operating at a rate between 9.95 Gb/s and 11.18 Gb/s.
The GTH transmitter offers bit widths of 16, 20, 32,40, 64, or 80.
These transmitter outputs asingle-channel differential current-mode logic (CML) output signal.
2.3 TEMAC
Ø 硬核数量
All of the Virtex-6 devices(except the XC6VLX760) have 4 TEMAC blocks.
Ø 支持接口类型
• MII
• GMII
• RGMII v1.3
• RGMII v2.0
• SGMII
• 1000BASE-X PCS/PMA
Ø 支持速率
• Tr i – speed
• 1000 Mbps
• 10/100 Mbps
Ø 支持SMI管理接口
2.4 SerialRapidIO
软核支持SRIO接口,数据速率1.25G、2.5G、3.75G
2.5 Power Supply
1.0V core voltage (-1, -2, -3 speed gradesonly)
Lower-power 0.9V core voltage option (-1Lspeed grade only)
3 子卡连接器标准
3.1 XilinxFMC标准
Ø LPC Connector
• 总共160pin
• 68 个用户定义的单端信号或者 34 个用户定义的差分对
• 1 个串行收发器对
• 时钟
• JTAG接口
• I2C接口
Ø HPC Connector
• 总共400pin
• 160 个用户定义的单端信号或者 80 个用户定义的差分对
• 10 个串行收发器对
• 时钟
• JTAG接口
• I2C接口
• 电源
3.2 AlteraHSMC标准
• 总共160pin
• 102 个用户定义的单端信号或者 51 个用户定义的差分对
• 时钟
• JTAG接口
• I2C接口
• 电源