8.编译自己的vo文件和testbench文件到work库即可仿真。
波形同上。
三.Modelsim库,Quartus II生成do文件代码分析及自行设计do文件
1.modelsim仿真库
以下是官方文档中的内容(更多内容请自行查看PDF文档)。
Design Library Overview
A design library is a directory or archive that serves as a repository for compiled design units.
The design units contained in a design library consist of VHDL entities, packages, architectures,and configurations; Verilog modules and UDPs (user-defined primitives); and SystemC modules. The design units are classified as follows:
• Primary design units — Consist of entities, package declarations, configuration
declarations, modulesUDPs, and SystemC modules. Primary design units within a given
library must have unique names.
• Secondary design units — Consist of architecture bodies, package bodies, and
optimized Verilog modules. Secondary design units are associated with a primary
design unit. Architectures by the same name can exist if they are associated with
different entities or modules.
Working Library Versus Resource Libraries
Design libraries can be used in two ways:
1. as a local working library that contains the compiled version of your design;
2. as a resource library.
The contents of your working library will change as you update your design and recompile. A resource library is typically static and serves as a parts source for your design. You can create your own resource libraries or they may be supplied by another design team or a third party(e.g., a silicon vendor).
Only one library can be the working library.
Any number of libraries can be resource libraries during a compilation. You specify which
resource libraries will be used when the design is compiled, and there are rules to specify in
which order they are searched (refer to Specifying Resource Libraries).
A common example of using both a working library and a resource library is one in which your gate-level design and testbench are compiled into the working library and the design references gate-level models in a separate resource library.
由上面的介绍可知,工作库只能有一个,而资源库则可以有许多。其中,在modelsim安装后有些库已经默认安装,例如IEEE库中包含预编译的synopsys的IEEE算法包,用于仿真加速等功能。这些库都有专用用途,初学者不宜更改。在仿真时,系统可以调用这些资源库来进行仿真,并且这些库是固定不变的。而工作库(默认的为work库,详见PDF文档)只有一个,它是用来把不同设计的编译文件等放进去,并且是不断更新变化的。
到处,我们初步了解了modelsim库的作用和概念。我们上面做的就是在modelsim中建立altera器件的仿真资源库,并且修改了ini文件使这些库是固定的(不必在不同设计中重复添加资源库,但是需要在每次打开Modelsim后添加搜索库,这两个是不同的概念)。
Modelsim仿真中会调用四种常用的仿真库:
(1)元件库,例如cycloneII元件库,在仿真中必用的特定型号的
FPGA/CPLD的库。
(2)primitive,调用altera的原语(primitive)设计仿真时需要;
(3)altera_mf,调用MagaFunction的设计仿真时需要;
(4)lpm,调用lpm元件的设计仿真时需要;
第一种元件库是进行时序仿真时不可缺少的资源库。后三种库是调用了相应的Altera设计模块进行设计时才必须用到的库。值得一提的是,在modelsim-altera的AE版本中,后三种库是已经编译好的,在modelsim-altera安装目录下altera文件夹中可以找到。
2.Quartus II生成do文件代码分析
注:读者需在之前对Modelsim命令有初步的了解,可参阅help文档。
打开仿真目录.test_simsimulation找到其中的test_sim_run_msim_gate_verilog.do文件,用记事本或其他文本编辑软件打开。完整代码如下:
- transcript on
- if ![file isdirectory verilog_libs] {
- file mkdir verilog_libs
- }
- vlib verilog_libs/cycloneii_ver
- vmap cycloneii_ver ./verilog_libs/cycloneii_ver
- vlog -vlog01compat -work cycloneii_ver {d:/altera/quartusii/quartus/eda/sim_lib/cycloneii_atoms.v}
- if {[file exists gate_work]} {
- vdel -lib gate_work -all
- }
- vlib gate_work
- vmap work gate_work
- vlog -vlog01compat -work work +incdir+. {test_sim.vo}
- vlog -vlog01compat -work work +incdir+D:/Programs/Quartus/test_sim/src {D:/Programs/Quartus/test_sim/src/sim.v}
- vsim -t 1ps +transport_int_delays +transport_path_delays -L cycloneii_ver -L gate_work -L work -voptargs="+acc" sim
- add wave *
- view structure
- view signals
- run -all
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下面扼要的介绍一下它的控制流程。首先调用它的时候它会检测当前目录下有没有Verilog_libs这个文件夹,没有的话创建;然后在该文件夹下创建了一个物理库cyclone_ver并把逻辑库cyclone_ver映射到前面的物理库;由于前面的工程很简单,只用到了一些基本部件,所以只编译了cycloneii_atoms.v文件到cyclone_ver库;之后又创建了一个gate_work的物理库并把逻辑库work库映射到gate_work;编译了网表文件和仿真激励文件到work库;启动仿真(注意-L后面的库,这条指令的作用和第二部分最后一步的添加搜索库是一样的,感兴趣可以打开Start simulation看一下);加窗口波形信号等后运行。
3.自行设计do文件
通过上面库的介绍和Quartus II代码的分析,可以自己写一下简单的do文件自动运行了。
下面的代码是我写的do文件,注意路径的修改和代码最后的回车符。
点击tools>tcl>execute macro..打开刚刚保存的do文件运行即可。
- cd D:/Programs/Quartus/test_sim/simulation/modelsim
- vlib work
- vmap work work
- vlog -vlog01compat -work work +incdir+. {test_sim.vo}
- vlog -vlog01compat -work work +incdir+D:/Programs/Quartus/test_sim/src {D:/Programs/Quartus/test_sim/src/sim.v}
- vsim -t 1ps +transport_int_delays +transport_path_delays -L cycloneii -L primitive -L lpm -L altera_mf -L work -voptargs="+acc" sim
- add wave *
- view structure
- view signals
- run -all
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附录:
测试程序:
- module test_sim(
- a,
- b,
- c
- );
- input a;
- input b;
- output c;
- assign c = a & ( ~ b);
- endmodule
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仿真激励:
- `timescale 1ns/1ps
- `define period 10
- module sim ();
- reg a;
- reg b;
- wire c;
- initial
- begin
- # (`period * 10) a = 1'b0;
- # (`period * 10) b = 1'b0;
- # (`period * 1000) $stop;
- end
- always #(`period * 10) a = {$random} % 2;
- always #(`period * 15) b = {$random} % 2;
- test_sim t_sim (
- .a(a),
- .b(b),
- .c(c)
- );
-
- endmodule
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