如何避免带DMA读传输的PIC24FJ256GB406 SPI主机字节之间的间隙？

像往常一样，论坛软件不允许我张贴。我必须拆分它，不能嵌入图像。悲伤：请手动点击附件。第一幅图像显示了带有正确数据的READ，但不希望出现间隙。（SPI-MOSI=SPI-SDO（TX），SPI-MISO=SPI-SDI（RX））正确的数据是0x3C，0x3F，0x78，0x6D，……如SPI RX Pin所示，在第二图像中显示了其他实验方法（使用TX作为DMA触发器）。逻辑分析仪“看到”正确的BYTEX03C，0x3F，0x78，0x6D…在SPI总线上，但是DMA将把附加的0xff作为第一个字节放入存储器。NULLW特性的文档说“对DMADST的每次写入都向DMASRC发起一个虚拟写入”。在第一幅图像中，可以正确地看到，在SPI-MOS上可以看到“对DMASRC的写入”。我（第0频道）。因此，在SPI-RX和伪写到SP-TX之间有一个“1”字节的“移位”。在第二个图像中，可以看出这种移位是2字节，这可能是由于错误的DMA触发条件。但我不知道哪一个是CORRET。下面的代码用于进行512字节的传输。NTYRX使用SPI RX或SPI TX作为DMA触发器，这个定义也用于SPI初始化，选择DMA触发器（SPI中断位）SPI初始化（部分）现在的问题是，是否有任何想法，我可以在DX触发时消除RX、O上的间隙问题。r在TX上进行DMA触发时，如何解决附加字节的问题。在这两种情况下，我的DMA触发器配置可能都是错误的，但我不知道哪里出错。最终的目标只是以8Mhz的速度进行传输。



      以下为原文

    As usual the forum software does not allow me to post. I have to split it and cannot embed the images.sad: Please click the attachments manually.
 
The first image shows the READ with correct data, but undesired gap.
(SPI-MOSI = SPI-SDO (TX) , SPI-MISO = SPI-SDI (RX) )
The correct data is 0x3C, 0x3F, 0x78, 0x6D,  ... as seen on the SPI RX pin
 
The other experimental method (using TX as DMA trigger) is shown in the second image.  The Logic Analyzer "sees" the correct bytes 
0x3c, 0x3F, 0x78, 0x6D ... on the SPI bus, but the DMA will place an additional 0xff as the first byte into the memory.
 
 
The documentation for the NULLW feature says "A dummy write is initiated to DMASRC for every write to DMADST".
In the first image, this can be seen correctly, the "write to DMASRC" can bee seen on the SPI-MOSI (channel 0). Thus there is a "shift" of +1 byte between SPI-RX and the dummy write to SPI-TX. 
In the second image it can be seen that this shift is +2 bytes, likely due to a wrong DMA trigger condition.
But I have no idea which one is corret.
 
The following code is used to do the 512 byte transfer.
The #define DMA_INT_RX either uses SPI RX or SPI TX as DMA trigger.
This #define  is also used for SPI initializiation choose the DMA trigger (SPI interrupt bit)
 
   
    DMACON = 0x0001;
 
    DMAH= 0x2800;
    DMAL= 0x0000;
    DMACH0 = 0;
    DMACH0bits.TRMODE=0; //Transfer mode
 
    DMACH0bits.SAMODE=0; //Source address fix
    DMACH0bits.DAMODE=1; // dest incr
    DMACH0bits.NULLW=1; // null write
 
    DMACH0bits.SIZE=1; // byte
    
    DMAINT0= 0x00;
    
    // for CHSEL see FRM Table 5-1
      
#ifdef DMA_INT_RX         // this one for
   DMAINT0bits.CHSEL = DMA_TRIG_SRC_SPI2_RECEIVE; //Trigger on SPI2 Receive
  _SPI2RXIF = 0;
#else
   DMAINT0bits.CHSEL = DMA_TRIG_SRC_SPI2_TRANSMIT; //Trigger on SPI2 Transmit
   _SPI2TXIF = 0;
#endif
    
    DMADST0= (WORD) pBuf;
    
    DMASRC0= (unsigned int)&SPI2BUFL;
    DMACNT0= wCount;
 
    // Clearing Channel 0 Interrupt Flag;
    IFS0bits.DMA0IF = false;
    
    //Enable DMA
    DMACONbits.DMAEN = 1;
    
     DMACH0bits.CHEN = 1;
  #if 0
      DMACH0bits.CHREQ = 1;   // to start dma, same as below
  #else
      SPI2BUFL = 0x0;               // to start dma
  #endif
          
    // real application will not wait for DMA to finish, this is only for testing
     while (! DMAINT0bits.DONEIF);
     while (!SPI2STATLbits.SRMT); // still busy, wait until really done
               
    DMACONbits.DMAEN = 0;

 
SPI initialization  (partial)
 

  SPI2CON1bits.MODE16 = 0; // byte mode
  SPI2CON1bits.MSTEN = 1;   //SPI  master,  CS is set manually
  SPI2CON1bits.CKP = 0;     
  SPI2CON1bits.CKE = 1;     
  SPI2CON1bits.ENHBUF = 0; 
  SPI2STATbits.SPIROV = 0; // clear the Receive overflow flag
 
  SPI2BRGLbits.BRG = 0; //  8 Mhz @ 32 Mhz cpu
  SPI2CON1bits.MCLKEN = 0;
 
   SPI2CON1Hbits.IGNROV = 1;
 
#ifdef DMA_INT_RX
  SPI2IMSKLbits.SPIRBFEN = 1; // interrupt if rx full
#else
  SPI2IMSKLbits.SPITBEN = 1;  // interrupt if tx empty
#endif
 
  SPI2CON1Lbits.SPIEN = 1;  // enable SPI2 peripheral

 
The question now is, whether there are any ideas how I can either remove the problem with the gaps while DMA triggering on RX, or how I can fix the problem with the additional byte while DMA triggering on TX.
In both cases my DMA trigger configuration might be wrong, but I have no more idea where I'm going wrong.
The ultimate goal is simply to do the transfer with full 8 Mhz speed. 

你打开了增强型缓冲模式-SPI2CON1.HANBUF吗？我现在可以看到你的代码了。不，你没有。你应该打开它。



      以下为原文

    Have you turned on the enhanced buffer mode - SPI2CON1.ENHBUF?
 
I can now see your code. No you didn't. You should turn it on.

这是我的“测试”没有改进，但我会再试一次。



      以下为原文

    It was one of my "tests" without improvement, but I will give it another try.
 

（忘记提及我的SPI初始化使用define SPI2STATbits SPI2STATLbits）[编辑：由于配置错误，ENHMODE的下列测试结果出错]仅仅将ENHMODE设置为1，而不是0，具有以下效果：对于RX方法上的DMA触发器，它增加了从0.5到0.5的间隙对于TX方法上的DMA触发器，它产生正确的数据，但是现在还有1.6us的间隙。



      以下为原文

    (Forgot to mention that my SPI initializations uses #define  SPI2STATbits  SPI2STATLbits)
 
[Edit: the following test results for ENHMODE were wrong due to a configuration error]
Just setting ENHMODE to 1 instead of 0  has the following effect:
For my DMA trigger on RX method it increases the gap from 0.5 to 1.6 us.
For my DMA trigger on TX method it results in correct data, but now there is also a gap of 1.6 us.
[Edit: the correct test result is, that ENHMODE does not solve the problem, and also does not change the timing]

 
 
 

在启动DMA之前，您可能需要在SPBIF中写入几个字节。这个想法是缓冲区中总是有一些东西，所以DMA传输不会减慢SPI。



      以下为原文

    You may need to write few bytes into the SPIBUF before you start DMA. The idea is that there's always something in the buffer, so that DMA transfers do not slow down SPI.

我第一次使用ENHMODE测试是错误的，因为我的配置错误。再次进行测试时，我观察到的差距越来越大。它们保持不变。然而，对于我的两种方法，ENHMODE似乎都不能解决空白的问题。我理解您通常向SPIBUF写入几个字节的想法，但具体来说我不清楚。我正在使用空写模式进行SPI DMA读取（即，DMA写入b b）。YTE作为对接收字节的反应，而不是ME）。我的理解是，SPI触发DMA本身，-我只需要第一次初始化它。而且我的纯DMA写例程没有这种间隙问题，它仅用于DMA读取。我是否应该更好地遵循使用SPI TX或RX事件的方法来解决我的问题？



      以下为原文

    My first tests with the proposed ENHMODE were wrong, due to a configuration error of mine.
Doing the tests again, my observation with increasing gaps was wrong. They stay the same.
However it looks as if ENHMODE does not solve the problem with the gaps, for none of my two approaches.
I understand your idea to write a few bytes to SPIBUF in general, but in detail it is not clear to me.
I'm doing a SPI DMA Read using the null write mode (i.e. the DMA writes a byte as a reaction to a received byte, not me).  My understanding is that the SPI triggers the DMA itself,- I have only to initialize it for the first time.
Also my pure DMA write routine does not have this problem with gaps, its only present for DMA Read. 

Should I better follow the approach to use the SPI TX or the RX event to solve my problem ?
 
 

经过更多的测试，我认为问题已经解决了。根据我的两种方法，我现在坚持“可能”更干净的方法，并使用RX中断作为DMA触发器（我没有设法改进另一种方法）——DMAINT0bit.CHSEL=DMA_TRIG_SRC_SPI2_RECEIVE（0x23）SPI2IMSKLbits.SPIRBFEN=1；//如果rx完全切换到增强模式，则中断确实改变了行为，即0.5us间隙一直存在。我的以下代码（如使用和原始文章中所示）开始DMA读取，但是对于所有512字节具有0.5us间隙，然后对其进行更改，以便将更多的字节写入SPI2BUFL。测试表明，写入一个附加字节就足够了，即总共两个字节。以下版本将消除不希望的0.5us空隙。奇怪的是，-这个（只）在没有增强模式的情况下工作。由于论坛软件再次不允许我添加图像：逻辑分析器跟踪显示SPI输出（TX）首先显示这两个虚拟字节0x42、0x43，然后是rELE 512数据字节（由空写入模式导致）。SPI In(RX)以实际512个数据字节加上最后2个虚拟字节(0xff)开始。因此，总线上的总字节数是514，而我的nand-flash仅“传送”512个字节。但是，由于DMA计数为512，因此只将512字节放入RAM内存中，这对我来说是有效的。



      以下为原文

    After some more testing I think the problem is solved.  From my two approaches I now stick with the "probably" more clean method and use the RX interrupt as DMA trigger (I did not manage to improve the other method)
     DMAINT0bits.CHSEL = DMA_TRIG_SRC_SPI2_RECEIVE     (0x23)
   SPI2IMSKLbits.SPIRBFEN = 1; // interrupt if rx full 
Simply switching to Enhanced mode did change the behaviour, i.e. the 0.5 us gap was always there.
My following code (as used and shown in original post) starts the DMA read, but has the 0.5 us gap for all 512 bytes
    DMACH0bits.CHEN = 1;
    SPI2BUFL = 0x0;               // to start dma


I then changed it in order to write some more bytes into SPI2BUFL.  Testing shows, it is sufficient to write one additional byte, i.e. two bytes in total. The following version will remove the undesired 0.5 us gaps.
    DMACH0bits.CHEN = 1;
    SPI2BUFL = 0x42;               // to start dma
    SPI2BUFL = 0x43;               // to start dma
And oddly enough,- this (only) works without  ENHANCED mode.
Since the forum software again does not allow me to add an image:  The Logic Analyzer trace shows for the SPI Out (TX) first these two dummy bytes 0x42, 0x43, then followed by the real 512 data bytes (resulting from the null write mode) .
The SPI In (RX) starts  with the real 512 data bytes plus 2 dummy bytes (0xff) at the end.
 
Thus the total number of bytes on the bus is 514, while my nand-flash only "delivers" 512 byte.
However since the DMA count is 512 and thus only places 512 bytes into my RAM memory, this works for me.
   Attached Image(s)

谢谢分享你的经验和解决方案，这很有帮助。



      以下为原文

    Thanks for sharing your experience and solution, it's very helpful.

在正常模式下（没有增强的缓冲区），它可以读取数据，并只在GAPP字节之间写入。由于没有增强缓冲器（MSSP模块）的芯片，避免间隙是绝对不可能的。然而，您的芯片还有较新的SPI模块，可能在这方面不同于旧的SPI模块。



      以下为原文

     In normal mode (without enhanced buffer) it can read data and write only during the gap between bytes. With the chips without enhanced buffer (and MSSP module) it's absolutely impossible to avoid gaps. However, your chip has yet newer SPI module, may be it is different from older ones in that respect.
 

我还没有走出困境。用8兆赫SPI时钟写得很好。我现在设法使用SPI MCLKEN模式和ReFCONL配置将其增加到12兆赫。问题又回来了！同样地，SPI DMA写函数没有问题，在12MHz下运行，字节之间没有间隙。SPI DMA读取，因为它在8MHz下工作，没有间隙，现在又具有0.8us的间隙。（这使我的512字节的总时间从512us增加到大约700us，因此没有增益，写3或4而不是2）。SPI TX的字节没有区别（没有缓冲区，所以只有两个字节离开SPI输出移位寄存器）。回到使用增强模式进行测试，写入例如4字节加上问题DMACH0bit.CHREQ=1；/SPI2BUFL=0x42；//启动dma SPI2BUFL=0x43；//启动dma SPI2BUFL=0x44；//启动dma SPI2BUFL=0x45；//启动dmaDMACH0bit.CHREQ=1；//强制DMAI在SPI输出管脚上看到这些第一个字节，但是实际上由于某种原因DMA传输没有启动。查看DMA计数寄存器它是511，也就是唯一传输的字节是由DMACH0bits强制传输的字节。开始吗？



      以下为原文

    I'm not out of the woods yet.
Works fine with 8 MHz SPI clock as written before. I now managed to increase it to 12 MHz using SPI MCLKEN mode and REFCONL configuration.  And the problem is back !
Again the SPI DMA write function has no problem, runs at 12 MHz without gaps between bytes.
SPI DMA read as it was working with 8 MHz without gaps, now has gaps again with 0.8 us.
(this makes the total time for my 512 bytes increase from 512 us to about 700 us, so no gain).
Writing 3 or 4 instead of 2 bytes to the SPI TX does not make a difference (There is no buffer, so only 2 bytes leave the SPI out shift register).
Reverting to testing with ENHANCED mode, writing e.g. 4 bytes PLUS issue DMACH0bits.CHREQ = 1;
      SPI2BUFL = 0x42;  // to start dma
      SPI2BUFL = 0x43;  // to start dma
      SPI2BUFL = 0x44;  // to start dma
      SPI2BUFL = 0x45;  // to start dma
      DMACH0bits.CHREQ = 1;   // force DMA
I see these first bytes on the SPI out pin, but actually the DMA transfer does not get started for some reason.
Also DMAINT0bits.DONEIF never gets true. Looking into the DMA count register it is 511, i.e. the only byte transferred is the one forced by DMACH0bits.CHREQ = 1;
I'm not sure whether to give up now and stick to the 8 MHz.
This NULL Write stuff seems to be tricky.
What is the difference between NORMAL and ENHANCE mode, which causes the DMA not to start ?
 

如果DMA与SPI相比使用不同的时钟，那么它本身可能是一个问题。关于如何用增强模式触发中断的文档最多也不清楚。因此，您需要试验一下何时调用中断。如果将模块设置为非常慢的速度，并且在设置了中断标志时，很容易做到这一点。然后你可以确定当Dout缓冲器中还有什么东西时，可以让DMA点火。您还需要确保NULL写不会溢出发送缓冲区。另一个想法是使用两个DMA信道-一个用于发送，一个用于接收。正如你已经写出来的，接收DMA应该适合在不造成任何延误。



      以下为原文

    If DMA uses different clock compared to SPI, it might be a problem in itself.
 
DMA works off interrupts. The documentation on how the interrupts are triggered with enhanced mode is not clear at best So, you would need to experiment on when the interrupts are invoked. It's easy to do if you set the module at the very slow speed and watch the interrupt flags as they're set. Then you figure out if it is possible to convince DMA to fire when there's still something in the out buffer. You also need to make sure that the NULL writes do not overflow the transmit buffer.
 
Another idea is to use two DMA channels - one for sending and one for reception. As you have your writes figured out, the receiving DMA should fit in without causing any delays.

我试图以非常慢的速度调查状态/中断标志。在等待DMA完成时，我读取有趣的位，并将它们输出到逻辑分析仪的分立管脚上。但是这看起来没有意义，所以我停止了这个评估。然后我尝试使用两个DMA通道，在开始的时候我想避免，因为NULL写特性看起来更简单更直接。我坚持“正常模式”，因为“增强模式”对我来说总是带来更多的问题，并且不能提高DMA传输的速度。挑战是使它与12MHz（SPI MCLKEN）一起工作。首先，我认为你是对的，用不同的时钟使用DMA和SPI可能是一个问题或者至少是更具挑战性的。再次，对于我的纯DMA Write，它在12MHz没有任何间隙的情况下工作没有问题。DMA读取的结果更难解释。我几乎达到12兆赫，只有小或没有差距，我需要一个更快的逻辑分析仪来详细说明。然而，数据本身被采样错误。我可以通过设置SMP:SPIx数据输入采样相位位来解决这个问题，但是这感觉更像是尝试和错误。经验教训：a）DMA写从来都不是问题，根本没有间隙。方法1使用空写模式，方法2使用两个DMA通道。在资源和功耗方面，我认为使用一个DMA比使用两个DMA要好。然而，我只有选择，因为我的PIC GB4具有SPI IGNORV配置位。据我所知，对于许多其他PIC，在执行READ时，必须始终使用两个DMA，因为任何Read Overflow都会停止传输。配置提示，我为TX配置DMA1，为RX配置DMA0。（SPI初始化参见前面的文章）为TX DMA通道配置RX DMA通道。最后开始传输并等待完成。“等待完成”仅用于测试目的，对于真正使用DMA中断的应用程序来说没有意义。



      以下为原文

    I tried to investigate the status / interrupt flags at very slow speed. While waiting for the DMA to finish, I read the interesting bits and output them on seperate pins to the Logic Analyzer. But this does not look meaningful, so I stopped this evaluation. 
Then I tried to use two DMA channels, which in the beginning I wanted to avoid, because the NULL Write Feature looked easier and more straight forward. I stick with "normal mode", because "enhanced mode" for me always brings more problems and does not improve the speed for the DMA transfer.
To sum up, it works well for my 8 MHz. The challenge was to get it work with 12 MHz (SPI MCLKEN).
First I think you are right, using DMA and SPI with different clocks might be a problem or at least more challenging.
Again, for my pure DMA Write it works without problems at 12 MHz without any gaps.  The results for DMA Read are more difficult to interpret. I almost reach the 12 MHz, only small or no gaps, I would need a faster Logic Analyzer to go into details. However the data itself gets sampled wrong. I can fix that by setting the SMP: SPIx Data Input Sample Phase bit, but this feels more like try and error.
 
Lessons learned: 
a) DMA Write never was a problem, no gaps at all.
b) For DMA Read I now have two methods, which work without gaps @ 8 MHz (FCy / 2).  Method 1 uses the NULL Write Mode, and Method 2 uses two DMA channels.  Looking at resources and power consumption I think using one DMA is better than using two DMAs.  However I only have the choice, because my PIC GB4 has the SPI IGNROV configuration bit. As far as I understand, for many other PICs you have always to use two DMAs, when performing a READ, because any Read Overflow would stop transmission also. 
 
For method 2 it was challenging for me to understand how to configure the two DMAs for performing a DMA read (only) transfer, here are some configuration hints for
I configure DMA1 for TX and DMA0 for RX.
(SPI initialization see previous posts)
 
Configuration for RX DMA channel

   DMACON = 0x0001;
 
    DMAH = 0x2800;
    DMAL = 0x0000;
    DMACH0 = 0;
    DMACH0bits.TRMODE=0;    // Transfer mode
 
    DMACH0bits.SAMODE=0;    // Source address fix
    DMACH0bits.DAMODE=1;    // dest incr
    DMACH0bits.NULLW=0;      // null write feature disabled
 
    DMACH0bits.SIZE=1;        // byte mode
    
    DMAINT0= 0x00;
    
    DMAINT0bits.CHSEL = DMA_TRIG_SRC_SPI2_RECEIVE;     
    _SPI2RXIF = 0;
 
    SPI2IMSKLbits.SPIRBFEN = 1;    // interrupt if rx full
    
    DMADST0= (WORD) pBuf;
    DMASRC0= (unsigned int)&SPI2BUFL;
    DMACNT0= wCount;
 
    IFS0bits.DMA0IF = false;   // Clearing Channel 0 Interrupt Flag;
       
    DMACONbits.DMAEN = 1;   
    DMACH0bits.CHEN = 1;

 
Configuration for TX DMA channel
 

    WORD wDummy = 0xff;
    DMACH1 = 0;
    DMAINT1 = 0;
    DMACH1bits.TRMODE=0;   // Transfer mode   

    DMACH1bits.SAMODE=0;  // Source address fix
    DMACH1bits.DAMODE=0;  // dest fix

    DMACH1bits.SIZE=1;  // byte mode
    DMAINT1bits.CHSEL = DMA_TRIG_SRC_SPI2_TRANSMIT; 
    
    DMASRC1= (WORD) &wDummy;
    DMADST1= (unsigned int)&SPI2BUFL;
    DMACNT1= wCount;

    _SPI2TXIF = 0;
    SPI2IMSKLbits.SPITBEN = 1;  // interrupt if tx empty
 
    DMACH1bits.CHEN = 1;

 
Finally start the transfer and wait for finish.  The 'wait' for finish is only for testing purposes and does not make sense for a real application, which will use the DMA interrupt instead.
 

SPI2_CS_ASSERT;
 
DMACH1bits.CHREQ = 1; 
while (!DMAINT1bits.DONEIF) ;
while (!SPI2STATLbits.SRMT);   // still busy, wait until really done
SPI2_CS_DEASSERT;

 

有一些传播延迟（在芯片内部和线路上）。理想情况下，在设置位之后，你会取样半个周期。在12MHz，这是42纳秒。除去10s的上升时间，剩下32ns。如果所有传播延迟（CLK通过线路+从延迟+MISOcoming back）的总和是32ns或更多，则系统无法维持12MHzSPI。这可能是因为这条线，但是即使是ChIPARE 10MHz的SPI规格最多。稍后的采样是一种修复方法。通常，所需的位设置在时钟边缘，并保持84纳秒，因为这（到下一个边缘）。正常取样是42ns，因为时钟边缘是针对周期的中间的。后期取样(SMP=1)将取样移动到84ns——您在取样时同时发出下一个时钟边缘。在这种情况下，奴隶无法改变它的比特，所以即使没有传播延迟，稍后的采样也可以工作。但是任何传播延迟都会使它更可靠。延迟采样从0到约72 ns的传播延迟是可以接受的。因此，将SMP设置为1并没有错。



      以下为原文

   


There's some propagation delay (both within the chip and on the line). Ideally, you sample half a cycle after the bit is set. At 12MHz this is 42 ns. Removing 10s rise time, this leaves you 32 ns. If the sum of all propagation delays (CLK through the line + slave delay + MISO coming back) is 32 ns or more, then the system cannot sustain 12MHz SPI. This could be because of the line, but even the SPI specs for the chip are 10MHz at most.
 
Later sampling is a way to fix that. Normally, the required bit is set at the clock edge and is held for 84 ns since that (to the next edge). Normal sampling is 42 ns since the clock edge and is aimed at the middle of the period. Late sampling (SMP=1) moves sampling to 84ns - you sample at the same time as you send out the next clock edge. There's no way the slave can change its bit before that, so later sampling would work even if there's no propagation delays. But any propagation delay at all will make it more reliable. Propagation delays from 0 to about 72 ns will be acceptable for late sampling. Therefore, there's nothing wrong with setting SMP to 1.