如何使用i2c接口和mcc生成代码

你是说你的代码被困在I2C1MeAxaGEIORIOR2C1YMasaQuestPuto循环中？你有一个范围可以探测这两条线吗？



      以下为原文

    You are saying that your code gets stuck in the I2C1_MESSAGE_FAIL or I2C1_MESSAGE_PENDING loop?
 
Do you have a scope that you can probe the two lines?

对。。当我调试时，我变成了2C1YMasaGeIORIORIO2C1MIXAGEJOPEN，所以我没有与奴隶的通信：（有什么想法吗？对不起，我的英语不是最好的



      以下为原文

    Yes.. when i debug i become I2C1_MESSAGE_FAIL or I2C1_MESSAGE_PENDING, 
So i do not have communication with the slave :(
Any idea?
 
Sorry my english is not the best

我相信你注册的TISISC是错误的，我也有同样的问题。MCC没有正确地生成它们。我相信您希望TRISC=0x18，而不是0x00.0x18=0 0 0 1 1 0 RC5 RC4 RC3 RC2 RC1 RC0您希望TRISC中的位是I2C使用的引脚的1。请告诉我，如果这样做，我可能已经看得太快了。



      以下为原文

    I believe your register setting for TRISC is wrong, I had the same problem. MCC doesn't generate them correctly. 
 
I believe you want TRISC = 0x18 instead of 0x00. 
 
0x18 = 0      0      0      1      1       0      0      0
                          RC5  RC4   RC3   RC2  RC1 RC0
 
You want the bits in TRISC to be a 1 for the pins you are using for I2C. Let me know if this works, I may have looked at it too quickly. 
 

谢谢你的回答，但这对我不起作用：TISISC是你问题的根源吗？或者你的解决方案是什么？



      以下为原文

    Thanks for your answer but it doesn't works for me :/
Were the TRISC the source of your problem? or what was your solution?

我认为这是我的问题的根源。另外，我必须把我使用的时钟源从锁相环换成高频内部振荡器。你有没有检查过你的线路，看看引脚是否至少驱动高/低？线路上有上拉电阻吗？



      以下为原文

    I think that was the source of my issues. Also I had to change the clock source I was using from a PLL to the HF internal oscillator. 
 
Have you ever probed your lines to see if the pins are at least driving high/low? 
 
do you have pull-up resistors on the lines?

嗯，我在16MHz不带锁相环的情况下使用iToSc。在线路中有4K7电阻+5V。不知道它为什么不工作。你能把你的配置位张贴出来吗？这些是我的：Apple PrimaMac配置文件FoC= iTIO67／/振荡器选择位-gt；内部振荡器块α-PrAPMA配置PLLCFG＝O//4x PLL使能& GT；直接使用μ* PrimaMac配置PICLLKEN＝ON／/主时钟使能位-GT；主时钟使能锁定监视器启用位-gt；故障安全时钟监视器禁用，γ-Pracm配置，IESO＝OF//内部/外部振荡器切换位-GT；振荡器切换模式禁用/ /CONT2L，PracMMA配置，PWRTEN = OF//上电定时器启用位-GT；停电定时器，禁用γ-PrimMA配置BBON＝SBordIS//Brown Outlook重置使能比特-GT；仅在硬件中启用Brown Outlook复位（SBORN被禁用）α-PrAPMA配置BRV＝190 / /棕色输出重置电压位-& VT，设置为1.90 V标称//CON2H H PARMAMA CONFIG WDTEN＝OF//看门狗定时器允许位-GT；看门狗定时器总是禁用。StdEn没有影响。{ Trac-TimeFigTPs＝32768 / /看门狗定时器后尺度选择位-gt；1:327 68 //CONT3Hα-PrAPMA配置CCP2MX＝PULTC1//CCP2 MUX位-GT；CCP2输入/输出与RC1πPracMA配置PPBEN = OF//PORTB A/D允许位-GT；PORTB & LT；5:0＆GT；PIN被配置为复位#pragma配置CCP3MX=PORTB5//P3A/CCP3多比特->P3A/CCP3输入/输出上的数字I/O与RB5#pragma配置HFOFST=ON//HFINTOSC快速启动>HFINTOSC输出和准备状态被振荡器稳定状态#pragma配置T3CMX=PORTC0//Timer3C3C不延迟。锁输入多重位>T3CKI在RC0#pragma配置P2BMX=PORTB5//ECCP2 B输出多重位->P2B在RB5\#pragma配置MCCP2B输出多重位->P2B在RB5\\#prpragma配置MCCPCPCP配置MCCPMCCPMCCPMCCP2MCCP2MCCP配置MCBMCCPMCBMCCLRE MCLRE=EX\\#prprprprpragma配置MCLCCCCCCCCCCCCCCCLMA MCLCPR配置MCLB配置MCLX/MCLX比特MCL堆栈full/下溢将导致重置#pragma config LVP=OFF//单电源ICSP启用位>单电源ICSP禁用#pragma config XINST=OFF//扩展指令集启用位>指令集扩展和索引寻址模式禁用（遗留模式）#pragma config DEBUG=OFF//Back地面调试->.bled//CONFIG5L#pragma配置CP0=OFF//代码保护块0->块0(000800-001FFFh)没有代码保护#pragma配置CP1=OFF//代码保护块1->块1(002000-003FFFh)没有代码保护#pragma配置CP2=OFF//代码保护块2->块2(002000-003FFFh)004000-005FFFh)没有代码保护#pragma配置CP3=OFF//代码保护块3->块3->(006000-007FFFh)没有代码保护//CONFIG5H#pragma配置CPB=OFF//引导块代码保护位->引导块(000000-0007FFh)没有代码保护#pragma配置CPD=OFF//数据EEPROM代码P保护位->数据EEPROM没有代码保护//CONFIG6L#pragma配置WRT0=OFF//写保护块0->块0(000800-001FFFh)没有写保护#pragma配置WRT1=OFF//写保护块1->块1(002000-003FFFh)没有写保护#pragma配置WRT2=OFF//写P保护块2->块2(004000-005FFFh)未写保护#pragma配置WRT3=OFF//写保护块3->块3(006000-007FFFh)未写保护//CONFIG6H#pragma配置WRTC=OFF//配置寄存器写保护位->配置寄存器(300000-3000FFh)无t写保护#pragma配置WRTB=OFF//引导块写保护位-&g t;引导块(000000-0007FFh)未写保护#pragma配置WRTD=OFF//数据EEPROM写保护位-&g t;数据EEPROM未写保护//CONFIG7L#pragma配置EBTR0=OFF//表读保护块0-&g块0(000800-001FFFh)不受其他块中执行的表读取的保护pragma配置EBTR1=OFF//表读取保护块1->块1(002000-003FFFh)不受其他块中执行的表读取的保护pragma配置EBTR2=OFF//表读取保护块2->块2004000-005FFFh)未被保护以免在其他块中执行的表读取#pragma config EBTR3=OFF//表读取保护块3->块3->块3(006000-007FFFh)未被保护以免在其他块中执行的表读取//CONFIG7H#pragma config EBTRB=OFF//引导块表读取保护位->BoOT块（000000 -000 07FFH）未被保护在其他块中执行的表读取



      以下为原文

    Mmm I'm using INTOSC at 16Mhz without PLL.
I have a 4K7 resistor to +5v in the lines.
No idea why it doesn't work.
Could you maybe post your configuration bits?
These are mine:
 
#pragma config FOSC = INTIO67 // Oscillator Selection bits->Internal oscillator block
#pragma config PLLCFG = OFF // 4X PLL Enable->Oscillator used directly
#pragma config PRICLKEN = ON // Primary clock enable bit->Primary clock enabled
#pragma config FCMEN = OFF // Fail-Safe Clock Monitor Enable bit->Fail-Safe Clock Monitor disabled
#pragma config IESO = OFF // Internal/External Oscillator Switchover bit->Oscillator Switchover mode disabled
// CONFIG2L
#pragma config PWRTEN = OFF // Power-up Timer Enable bit->Power up timer disabled
#pragma config BOREN = SBORDIS // Brown-out Reset Enable bits->Brown-out Reset enabled in hardware only (SBOREN is disabled)
#pragma config BORV = 190 // Brown Out Reset Voltage bits->VBOR set to 1.90 V nominal
// CONFIG2H
#pragma config WDTEN = OFF // Watchdog Timer Enable bits->Watch dog timer is always disabled. SWDTEN has no effect.
#pragma config WDTPS = 32768 // Watchdog Timer Postscale Select bits->1:32768
// CONFIG3H
#pragma config CCP2MX = PORTC1 // CCP2 MUX bit->CCP2 input/output is multiplexed with RC1
#pragma config PBADEN = OFF // PORTB A/D Enable bit->PORTB<5:0> pins are configured as digital I/O on Reset
#pragma config CCP3MX = PORTB5 // P3A/CCP3 Mux bit->P3A/CCP3 input/output is multiplexed with RB5
#pragma config HFOFST = ON // HFINTOSC Fast Start-up->HFINTOSC output and ready status are not delayed by the oscillator stable status
#pragma config T3CMX = PORTC0 // Timer3 Clock input mux bit->T3CKI is on RC0
#pragma config P2BMX = PORTB5 // ECCP2 B output mux bit->P2B is on RB5
#pragma config MCLRE = EXTMCLR // MCLR Pin Enable bit->MCLR pin enabled, RE3 input pin disabled
// CONFIG4L
#pragma config STVREN = ON // Stack Full/Underflow Reset Enable bit->Stack full/underflow will cause Reset
#pragma config LVP = OFF // Single-Supply ICSP Enable bit->Single-Supply ICSP disabled
#pragma config XINST = OFF // Extended Instruction Set Enable bit->Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
#pragma config DEBUG = OFF // Background Debug->Disabled
// CONFIG5L
#pragma config CP0 = OFF // Code Protection Block 0->Block 0 (000800-001FFFh) not code-protected
#pragma config CP1 = OFF // Code Protection Block 1->Block 1 (002000-003FFFh) not code-protected
#pragma config CP2 = OFF // Code Protection Block 2->Block 2 (004000-005FFFh) not code-protected
#pragma config CP3 = OFF // Code Protection Block 3->Block 3 (006000-007FFFh) not code-protected
// CONFIG5H
#pragma config CPB = OFF // Boot Block Code Protection bit->Boot block (000000-0007FFh) not code-protected
#pragma config CPD = OFF // Data EEPROM Code Protection bit->Data EEPROM not code-protected
// CONFIG6L
#pragma config WRT0 = OFF // Write Protection Block 0->Block 0 (000800-001FFFh) not write-protected
#pragma config WRT1 = OFF // Write Protection Block 1->Block 1 (002000-003FFFh) not write-protected
#pragma config WRT2 = OFF // Write Protection Block 2->Block 2 (004000-005FFFh) not write-protected
#pragma config WRT3 = OFF // Write Protection Block 3->Block 3 (006000-007FFFh) not write-protected
// CONFIG6H
#pragma config WRTC = OFF // Configuration Register Write Protection bit->Configuration registers (300000-3000FFh) not write-protected
#pragma config WRTB = OFF // Boot Block Write Protection bit->Boot Block (000000-0007FFh) not write-protected
#pragma config WRTD = OFF // Data EEPROM Write Protection bit->Data EEPROM not write-protected
// CONFIG7L
#pragma config EBTR0 = OFF // Table Read Protection Block 0->Block 0 (000800-001FFFh) not protected from table reads executed in other blocks
#pragma config EBTR1 = OFF // Table Read Protection Block 1->Block 1 (002000-003FFFh) not protected from table reads executed in other blocks
#pragma config EBTR2 = OFF // Table Read Protection Block 2->Block 2 (004000-005FFFh) not protected from table reads executed in other blocks
#pragma config EBTR3 = OFF // Table Read Protection Block 3->Block 3 (006000-007FFFh) not protected from table reads executed in other blocks
// CONFIG7H
#pragma config EBTRB = OFF // Boot Block Table Read Protection bit->Boot Block (000000-0007FFh) not protected from table reads executed in other blocks

SSP2STAT=0x00；SSP2CON1=0x0；SSP2CON3=0x0；SSP2ADD=0x03；PIR2位.SSP2IF=0x03；PIR2比特.SSP2P2IF=0；PI2比特.SSP2IF=0；PIE2比特.SSP2IE=0;PIE2bits.SSP2IE=1；LATC=0XX=0XX=0X00；LATC=0x00=0x00；WPUA=0x00；WPUC=0x00；WPUC=0x00=0x00；ANSELA=0x37；ANSELC=0x37；ANSELC=0x05；ANSELC=0x05；0x05；TRISC=0gt;MSSP2:SCL2;RC1PPSbits.RC1PPS=0x1B;t;MSSP2:SDA2;#pragma config FEXTOSC=OFF//FEXTOSC外部振荡器模式选择位->未启用的振荡器#pragma config RSTOSC=HFINT1//COSC位的断电默认值->HFINTOSC#pragma config CLKOUTEN=OFF//Clock Out Enable bit-> CLKOUT功能被禁用；I/O或oscOSC2#pragma config CSWEN=ON//Clock Switch Enable bit->写入NOSC和NDIV上的振荡器功能#pragma config FCMEN=ON//Fail-Safe Clock Monitor Enable->Fail-Safe Clock Monitor Enable->Fail-Safe Clock Monitor Enable//CONFIG2#pragma config MCLRE=ON//Master Clear Enable bit-> MCLR/VPP引脚功能离子是MCLR；弱上拉启用#pragma配置PWRTE=OFF//上电定时器启用位->PWRT禁用#pragma配置WDTE=OFF//看门狗定时器启用位->WDT禁用；SWDTEN被忽略#pragma配置LPBOREN=OFF//低功率BOR启用位->ULPBOR禁用#pragma配置BOREN=ON//Brown-out Reset Enable位->Brown-out Reset启用，SBOREN位忽略#pragma配置BORV=LOW//Brown-out Reset电压选择位->Brown-out电压（Vbor），设置为2.45V#pragma配置PPS1WAY=ON//PPSLOCK位单向设置Enable位-> PPSLOCK位只能被清除和设置一旦；在一个清除/设置周期#pragma配置STVREN=ON//堆栈溢出/下溢复位启用位>堆栈溢出或下溢将导致复位#pragma配置DEBUG=OFF//调试器启用位>后台调试器禁用//CONFIG3#pragma配置WRT=OFF//用户NVM自写保护位->写保护#pragma配置LVP=ON//低压编程启用位->低压编程启用。MCLR/VPP引脚功能是MCLR。忽略MCLRE配置位。//CONFIG4#pragma配置CP=OFF//用户NVM程序内存代码保护位->用户NVM代码保护禁用#pragma配置CPD=OFF//数据NVM内存代码保护位->数据NVM代码保护禁用



      以下为原文

    SSP2STAT = 0x00;
SSP2CON1 = 0x28;
SSP2CON3 = 0x00;
SSP2ADD = 0x03;
PIR2bits.SSP2IF = 0;
PIE2bits.SSP2IE = 1;
 
LATA = 0x00;
LATC = 0x00;
WPUA = 0x00;
WPUC = 0x00;
ANSELA = 0x37;
ANSELC = 0x05;
TRISC = 0x3A; 
TRISA = 0x13;
 
RC4PPSbits.RC4PPS = 0x1A;   //RC4->MSSP2:SCL2;
RC1PPSbits.RC1PPS = 0x1B;   //RC1->MSSP2:SDA2;
 
#pragma config FEXTOSC = OFF // FEXTOSC External Oscillator mode Selection bits->Oscillator not enabled
#pragma config RSTOSC = HFINT1 // Power-up default value for COSC bits->HFINTOSC
#pragma config CLKOUTEN = OFF // Clock Out Enable bit->CLKOUT function is disabled; I/O or oscillator function on OSC2
#pragma config CSWEN = ON // Clock Switch Enable bit->Writing to NOSC and NDIV is allowed
#pragma config FCMEN = ON // Fail-Safe Clock Monitor Enable->Fail-Safe Clock Monitor is enabled
// CONFIG2
#pragma config MCLRE = ON // Master Clear Enable bit->MCLR/VPP pin function is MCLR; Weak pull-up enabled
#pragma config PWRTE = OFF // Power-up Timer Enable bit->PWRT disabled
#pragma config WDTE = OFF // Watchdog Timer Enable bits->WDT disabled; SWDTEN is ignored
#pragma config LPBOREN = OFF // Low-power BOR enable bit->ULPBOR disabled
#pragma config BOREN = ON // Brown-out Reset Enable bits->Brown-out Reset enabled, SBOREN bit ignored
#pragma config BORV = LOW // Brown-out Reset Voltage selection bit->Brown-out voltage (Vbor) set to 2.45V
#pragma config PPS1WAY = ON // PPSLOCK bit One-Way Set Enable bit->The PPSLOCK bit can be cleared and set only once; PPS registers remain locked after one clear/set cycle
#pragma config STVREN = ON // Stack Overflow/Underflow Reset Enable bit->Stack Overflow or Underflow will cause a Reset
#pragma config DEBUG = OFF // Debugger enable bit->Background debugger disabled
// CONFIG3
#pragma config WRT = OFF // User NVM self-write protection bits->Write protection off
#pragma config LVP = ON // Low Voltage Programming Enable bit->Low Voltage programming enabled. MCLR/VPP pin function is MCLR. MCLRE configuration bit is ignored.
// CONFIG4
#pragma config CP = OFF // User NVM Program Memory Code Protection bit->User NVM code protection disabled
#pragma config CPD = OFF // Data NVM Memory Code Protection bit->Data NVM code protection disabled

谢谢你的支持！但我还是有问题…



      以下为原文

    Thanks for your support!! but i still having the problem..

跟踪Atttp://www. McCHIP.COM/FUMMS/M944 121.ASPX



      以下为原文

    follows up at
http://www.microchip.com/forums/m944121.aspx