ad9516-4时钟芯片配置注意事项

1，ad9516-4时钟芯片配置，通信协议为SPI接口协议，时序比较简单，重点是给该芯片寄出去写入合适的配置信息，让其正常工作
2，ad9516-4时钟芯片的外围电路中，环路滤波器的设计比较重要，看参考开发板或者芯片手册，选择合适的电阻电容值
3，在调试时，PFD参数可以更改，当配置正确，时序正确是，还是出不来理想的时钟信号时，可以改变PFD参数试一下，如：16M变为4M，4M变为1M，降低PFD值重新配置
4，写FPGA程序的时候，可以将配置值存储在一个rom里，规划好地址空间，便于配置和检查更新等
5，附vhdl源代码，可供参考，rom配置信息请自己琢磨，可以交流
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENtiTY AD9516_init IS
PORT(clk : in std_logic; -----for 16M
     rst : in std_logic; -----reset signal ,low active,from pll0.
     
     sdo : in std_logic;    ----to read register
     sclk: out std_logic;   ---same as clk
     cs  : out std_logic;   ---low active,to write or read
     sdio: inout std_logic; ----to write register
     
sync   : out std_logic;     --manual synchronizations,not use when '1'
pd     : out std_logic;     --powndown,low active
ref_sel: out std_logic;     --choose ref1,when '0';
refmon : in std_logic;
ld     : in std_logic;
status : in std_logic;
AD9516_ready: out std_logic
     );
END ENTITY;
ARCHITECTURE BEHAVE OF AD9516_init IS
    signal AD9516_ready_tmp: std_logic;
    signal cnt: integer range 0 to 1023;             ----control address and cs output
    signal address_c: std_logic_vector(9 downto 0);  ----control rom output
    signal clk_rom: std_logic;                       -----not as clk
    signal cnt_cal: integer range 0 to 200000;     ----need 8800*PDF cycles=140800Tclk
signal ld_rising: std_logic;                   ----ld ��***��Ϊ��ʱ����10�����Ҹ�clk���ȶ�

    signal sub_wire: std_logic;                      -----buffer ,rom data output
    component rom_ad9516_4
        PORT
   (
   address : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
   clock : IN STD_LOGIC ;
   q : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
   );
end component;

BEGIN
    R1: rom_ad9516_4 port map(address=>address_c,clock=>clk_rom,q(0)=>sub_wire);

AD9516_ready <= AD9516_ready_tmp;
sclk <= clk;
clk_rom <= not clk;
sync <= '1';
    pd   <= '1';
ref_sel <= '0';
    sdio <= sub_wire;
   
P2: process(clk_rom,rst) is ----control address and cs output,main process
   
    begin
        if(rst='0') then
     --AD9516_ready_tmp<='0';
            cnt<=0;
            address_c<="0000000000";
            cs<='1';
        else
if(rising_edge(clk_rom)) then
if(cnt=1023) then
  --AD9516_ready_tmp<='1';
cnt<=1000;  ------bigger than 657 (658---1022)
else
  --AD9516_ready_tmp<=AD9516_ready_tmp;
cnt<=cnt+1;
end if;
            
case cnt is
  ----initialize
when 0 to 7 => cs<='1';address_c<="0000000000";                        
when 8 to 9 => cs<='1';address_c<=conv_std_logic_vector(cnt-8,10);

----translate data pll
when 10 to 145 => cs<='0';address_c<=conv_std_logic_vector(cnt-8,10);  
when 146 to 153 => cs<='1';address_c<=conv_std_logic_vector(cnt-8,10);

----vco divider and vco calibration
--vco divider and intiate vco calibration
when 154 to 177 => cs<='0';address_c<=conv_std_logic_vector(cnt-8,10);
when 178 to 185 => cs<='1';address_c<=conv_std_logic_vector(cnt-8,10);
when 186 to 217 => cs<='0';address_c<=conv_std_logic_vector(cnt-8,10);
when 218 to 225 => cs<='1';address_c<=conv_std_logic_vector(cnt-8,10);
when 226 to 249 => cs<='0';address_c<=conv_std_logic_vector(cnt-8,10);
when 250 to 257 => cs<='1';address_c<=conv_std_logic_vector(cnt-8,10);
when 258 to 281 => cs<='0';address_c<=conv_std_logic_vector(cnt-8,10);
when 282 to 289 => cs<='1';address_c<=conv_std_logic_vector(cnt-8,10);
--vco calibration
when 290 to 313 => cs<='0';address_c<=conv_std_logic_vector(cnt-8,10);
when 314 to 321 => cs<='1';address_c<=conv_std_logic_vector(cnt-8,10);
when 322 to 345 => cs<='0';address_c<=conv_std_logic_vector(cnt-8,10);
when 346 to 353 => cs<='1';address_c<=conv_std_logic_vector(cnt-8,10);
when 354 to 377 => cs<='0';address_c<=conv_std_logic_vector(cnt-8,10);
when 378 to 385 => cs<='1';address_c<=conv_std_logic_vector(cnt-8,10);
when 386 to 409 => cs<='0';address_c<=conv_std_logic_vector(cnt-8,10);
when 410 to 417 => cs<='1';address_c<=conv_std_logic_vector(cnt-8,10);

----channel divider 3 and 4
when 418 to 513 => cs<='0';address_c<=conv_std_logic_vector(cnt-8,10);
when 514 to 521 => cs<='1';address_c<=conv_std_logic_vector(cnt-8,10);
when 522 to 545 => cs<='0';address_c<=conv_std_logic_vector(cnt-8,10);
when 546 to 553 => cs<='1';address_c<=conv_std_logic_vector(cnt-8,10);

----lvds outputs
when 554 to 601 => cs<='0';address_c<=conv_std_logic_vector(cnt-8,10);
when 602 to 609 => cs<='1';address_c<=conv_std_logic_vector(cnt-8,10);
when 610 to 633 => cs<='0';address_c<=conv_std_logic_vector(cnt-8,10);
when 634 to 641 => cs<='1';address_c<=conv_std_logic_vector(cnt-8,10);

----fine delay adjust
when 642 to 753 => cs<='0';address_c<=conv_std_logic_vector(cnt-8,10);
when 754 to 761 => cs<='1';address_c<=conv_std_logic_vector(cnt-8,10);
when 762 to 785 => cs<='0';address_c<=conv_std_logic_vector(cnt-8,10);
        when 786 to 793 => cs<='1';address_c<=conv_std_logic_vector(cnt-8,10);

----read back information:write 0x000,0x004,0x023; read address 0x01f
--when 794 to 817 => cs<='0';address_c<=conv_std_logic_vector(cnt-8,10);
--when 818 to 841 => cs<='0';address_c<=conv_std_logic_vector(cnt-8,10);
--when 842 to 865 => cs<='0';address_c<=conv_std_logic_vector(cnt-8,10);
--when 866 to 889 => cs<='0';address_c<=conv_std_logic_vector(cnt-8,10);

----cs pull high finish AD9516_4
when others => cs<='1'; address_c<="0000000000";
end case;
            end if;
end if;
    end process;   
P3: process(clk_rom,rst) is ----control ad9516_ready output
   
    begin
        if(rst='0') then
     AD9516_ready_tmp<='0';
            cnt_cal<=0;
elsif(clk_rom'event and clk_rom='1') then
     if(ld_rising='1') then
         if(cnt_cal=200000) then
       AD9516_ready_tmp<='1';
    cnt_cal<=0;
   else
       AD9516_ready_tmp<=AD9516_ready_tmp;
    cnt_cal<=cnt_cal+1;
end if;
end if;
end if;
end process;

P4: process(clk_rom,rst) is  ----ld rising detect
    begin
        if(rst='0') then
     ld_rising<='0';
elsif(clk_rom'event and clk_rom='1') then
     if(ld='1') then
   ld_rising<='1';
else
   ld_rising<=ld_rising;
end if;
end if;
    end process;  
END ARCHITECTURE;