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嗨,在某些校准标准中,校准套件具有负电感系数。
如果它只是系数集的某些部分,如L1,L2等,在短期内不难理解。 但是,对于某些晶圆上校准标准,前面只有一个负电感,比方说LOAD标准。 在这一点上,由于这些原因,事情变得很奇怪:1。通常情况下,串联电感或并联电容可视为一条传输线,分别具有无限/ 0特性阻抗。 但是,具有负值的电感器,我们应该将其视为串联负电感还是分流正电容? 2.此电感/电容转换仅在某个特定频率下工作。 我们应该以哪种频率进行这样的翻译? 在实际应用中,如果将负电感视为LOAD标准的系数,将其转换为负延迟时间是否正确? 否则,我只能考虑将其转换为正值,但在不同频率下不同,这意味着产生分散效应。 我不确定这里的最佳做法是什么,似乎我们的校准存在一些问题。 所以我想让这里的基本理论更加清晰。 在此先感谢您的回复! 此致,NL 以上来自于谷歌翻译 以下为原文 Hi, In some calibration standards the cal kits have negative inductance coefficients. It is not hard to understand if it is only some parts of coefficient set, like L1, L2 etc, in the short stand. However, for some on-wafer calibration standard, there is only one negative inductance is placed in front of, let's say, LOAD standard. At this point, things become strange, for these reason in my point of view: 1. Normally a series inductor or a shunt capacitor can be seen as a piece of transmission line, with infinite/0 characteristic impedance respectively. However, an inductor with negative value, should we consider it as a series negative inductor, or a shunt positive capacitor? 2. This inductor/capacitor translation only works at some specific frequency. At which frequency should we perform such a translation? In real application, if a negative inductance is considered as the coefficient of a LOAD standard, is it correct to translate it to a negative delay time? Otherwise, I could only consider translate it to a positive value, but different at different frequency, which is implying a dispersive effect. I am not sure what is the best practice here and it seems there is some problem with our calibration. So I would like to make the fundamental theory here clearer. Thanks in advance for any reply! Regards, NL |
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我注意到你没有提到你有哪种型号的分析仪。
我可以肯定地说,像PNA这样的更现代的分析仪不会考虑电感系数,除非标准的类型被指示为短路。 对于与网络分析仪一起使用的所有软件包,情况可能并非如此,但对于现代安捷伦分析仪的固件,情况就是如此。 在PNA系列中,前面板接口仅允许您在已选择短路时指定电感系数。 用于指定校准套件的PNA远程(SCPI)命令允许用户在用户指示标准类型之前或之后输入电感系数,但仅在将类型指定为短时才使用它们。 以上来自于谷歌翻译 以下为原文 I noticed you didn't mention which model of analyzer(s) you have. I can say with certainty that more modern analyzers such as PNA for example do not take inductance coefficients into account unless the standard's type is indicated to be a Short. Perhaps that may not be the case with all software packages for use with network analyzers, but for the firmware of the modern Agilent analyzers it is the case. On the PNA family the front-panel interface only lets you specify inductance coefficients when you've already selected that it's a Short. The PNA's remote (SCPI) commands for specifying a cal kit do allow users to enter inductance coefficients before or after the user indicates the standard's Type, but they only get used when the Type's been specified as Short. |
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uwyywefwd 发表于 2019-7-1 13:11 感谢您的回复。 让我澄清一下。 我们的VNA是8720ES,它没有非线性电感模型,更符合SHORT标准。 我已经在这个论坛上提出了一些问题。 基本上我们的解决方案,如此处所建议的,是计算新的偏移延迟/偏移损耗值以考虑电感项。 现在我们面临的问题是计算晶圆上的cal-kit系数。 对于LOAD标准,存在一系列负电感值,应该将其转换为延迟项,以便我们可以将其输入到VNA中。 我们不确定的是我们如何为负电感制作等效传输线。 在我看来,这样的TL可能是分散的......问候,楠 以上来自于谷歌翻译 以下为原文 Thanks for your kind reply. Let me clarify a little bit. The VNA we have is a 8720ES, which does not have non-linear inductance model more SHORT standard. I have already asked some questions at this forum. Basically our solution, as suggested here, is to compute a new offset delay/offset loss value to account for the inductance term. Now the problem we are facing is to compute an on-wafer cal-kit coefficients. For the LOAD standard there is a series negative inductance value, which should be translated to a delay term so that we can input it into the VNA. What we are not sure is how we could make an equivalent transmission line for the negative inductance. Such a TL may be dispersive in my point of view... Regards, Nan |
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您可以使用以下近似法对电感器与电阻器串联建模:使偏移线的偏移量Zo为>>电阻器值。
如果电阻为50欧姆,则使偏移Zo> 500欧姆,然后计算器偏移延迟= L /(偏移Zo)。 负电感=负延迟。 抵消损失应为零。 固定载荷或任意阻抗设置允许您通过这种方式定义偏移。 对于固定负载,终端被认为是50欧姆或系统阻抗。 对于任意阻塞,终止可以定义为任何实际值。 以上来自于谷歌翻译 以下为原文 You can model an inductor in series with a resistor by using the following approximation: Make the offset Zo of the offset line >> the resistor value. If the resistor is 50 ohms, make offset Zo >500 ohms then calculator offset delay = L/(offset Zo). Negative inductance = negative delay. Offset loss should be zero. The fix load or arbitrary impedance set up allow you to define the offsets that way. For a fixed load the termination is assued to be 50 ohms or system impedance. For an arbitrary impdance, the termination can be defined as any real value. |
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60user22 发表于 2019-7-1 13:41 那么你的意思是应用程序中的负延迟值是否正常? 目前我们在8720ES系列VNA上使用负值。 但有人认为负值不适用于这个旧模型,需要以某种方式转化为正值。 我们不确定如何做到这一点所以我在这里要求一些建议。 在校准基板系数文件中,对于Load标准,有三个选项可供选择。 它表示1.6fF或-4.0pH或5欧姆& 0.0081 ps。 似乎-4.0pH以某种方式转换为1.6fF,并且该1.6fF被转换为0.0081ps,具有5欧姆作为特征阻抗。 我完全不知道这个-4.0pH是如何与这个1.6fF相关的...这里需要进一步解释。 谢谢! 此致,南 以上来自于谷歌翻译 以下为原文 So you mean a negative delay value is OK in the application? Currently we are using negative values on a 8720ES series VNA. But someone suggests negative value is not usable on this old model and need to be translated to a positive value somehow. We are not sure how this can be done so I am asking for some advice here. In a calibration substrate coefficient file, for the Load standard, there are three options to choose. It says 1.6fF or -4.0pH or 5 Ohm & 0.0081 ps. It seems that the -4.0pH is translated to 1.6fF somehow, and this 1.6fF is translated to 0.0081ps with 5 Ohm as characteristic impedance. I totally have no idea how this -4.0pH is related to this 1.6fF... Some further explanation is needed here. Thanks! Regards, Nan |
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jiaolesu 发表于 2019-7-1 13:56 > {quote:title = linan0827写道:} {quote}>所以你的意思是负延迟值在应用程序中是否正常? >>目前我们在8720ES系列VNA上使用负值。 但有人认为负值不适用于这个旧模型,需要以某种方式转化为正值。 我们不确定如何做到这一点所以我在这里要求一些建议。 即使在那个旧模型上也没有任何错误。 我使用的是8720D,甚至比8720ES还要老。 看到这个线程对于“开放式”校准标准,可以有一个负偏移和电容吗? 特别是安捷伦的Joel Dunsmore博士于2013年1月1日@ 10:54 PM发表的评论。 +如果你设置标准(或测试连接器)有一些衰退,并参考测试引脚,那么你将合理地有一些负偏移。+如果我是你,我会忘记负电感,但使用负偏移延迟 。 戴夫 以上来自于谷歌翻译 以下为原文 > {quote:title=linan0827 wrote:}{quote} > So you mean a negative delay value is OK in the application? > > Currently we are using negative values on a 8720ES series VNA. But someone suggests negative value is not usable on this old model and need to be translated to a positive value somehow. We are not sure how this can be done so I am asking for some advice here. There is nothing wrong in having a negative delay, even on that old model. I use an 8720D, which is even older than the 8720ES. See this thread Can one have a negative offset and capacitance for an "open" cal standard? and in particular this comment from Dr. Joel Dunsmore of Agilent posted on January 1st, 2013 @ 10:54 PM. +If you setup you standards (or test connector) to have some recession, and reference to the test pin, then you will reasonably have some negative offset.+ If I were you, I would forget about negative inductances, but use negative offset delays. Dave |
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60user7 发表于 2019-7-1 14:03 谢谢戴夫的解释! 以上来自于谷歌翻译 以下为原文 Thanks Dave for your explanation! |
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