如何帮助pic24fj128ga202 ADC？

嗨，我有麻烦让ADC工作在PIC24FJ128GA202上读取一个引脚上的电压。我注意到数据表上写着AVSS和AVDD作为参考，而我的28个引脚包没有这些引脚，而带有更多引脚的包没有。如果我配置它使用AVDD/AVSS作为参考，它会使用VDD/VSS吗？我已经尝试了手动采样和自动设置SAMP位。



      以下为原文

    Hi, I am having trouble getting ADC to work on PIC24FJ128GA202 to read the voltage on a pin. I notice the datasheet says AVSS and AVDD as reference, and my 28 pin package doesnt have these pins while the package with more pins does. If i configure it to use AVDD/AVSS as reference, will it use VDD/VSS?

I have tried it on manual sampling and automatic set SAMP bit

/*
* File:   helloworld.c
* Author: Chenxi_2
*
* Created on July 26, 2016, 3:31 PM
*/
#define _XTAL_FREQ 7370000      //29480000
#define FOSC  7370000            //29480000
#define FCY FOSC/2


// CONFIG4
#pragma config DSWDTPS = DSWDTPS1F      // Deep Sleep Watchdog Timer Postscale Select bits (1:68719476736 (25.7 Days))
#pragma config DSWDTOSC = LPRC          // DSWDT Reference Clock Select (DSWDT uses LPRC as reference clock)
#pragma config DSBOREN = ON             // Deep Sleep BOR Enable bit (DSBOR Enabled)
#pragma config DSWDTEN = ON             // Deep Sleep Watchdog Timer Enable (DSWDT Enabled)
#pragma config DSSWEN = ON              // DSEN Bit Enable (Deep Sleep is controlled by the register bit DSEN)
#pragma config PLLDIV = DISABLED        // USB 96 MHz PLL Prescaler Select bits (PLL Disabled)
#pragma config I2C1SEL = DISABLE        // Alternate I2C1 enable bit (I2C1 uses SCL1 and SDA1 pins)
#pragma config IOL1WAY = OFF            // PPS IOLOCK Set Only Once Enable bit (The IOLOCK bit can be set and cleared using the unlock sequence)

// CONFIG3
#pragma config WPFP = WPFP127           // Write Protection Flash Page Segment Boundary (Page 127 (0x1FC00))
#pragma config SOSCSEL = OFF            // SOSC Selection bits (Digital (SCLKI) mode)
#pragma config WDTWIN = PS25_0          // Window Mode Watchdog Timer Window Width Select (Watch Dog Timer Window Width is 25 percent)
#pragma config PLLSS = PLL_FRC          // PLL Secondary Selection Configuration bit (PLL is fed by the on-chip Fast RC (FRC) oscillator)
#pragma config BOREN = ON               // Brown-out Reset Enable (Brown-out Reset Enable)
#pragma config WPDIS = WPDIS            // Segment Write Protection Disable (Disabled)
#pragma config WPCFG = WPCFGDIS         // Write Protect Configuration Page Select (Disabled)
#pragma config WPEND = WPENDMEM         // Segment Write Protection End Page Select (Write Protect from WPFP to the last page of memory)

// CONFIG2
#pragma config POSCMD = NONE            // Primary Oscillator Select (Primary Oscillator Disabled)
#pragma config WDTCLK = LPRC            // WDT Clock Source Select bits (WDT uses LPRC)
#pragma config OSCIOFCN = OFF           // OSCO Pin Configuration (OSCO/CLKO/RA3 functions as CLKO (FOSC/2))
#pragma config FCKSM = CSDCMD           // Clock Switching and Fail-Safe Clock Monitor Configuration bits (Clock switching and Fail-Safe Clock Monitor are disabled)
#pragma config FNOSC = FRC              // Initial Oscillator Select (Fast RC Oscillator (FRC))
#pragma config ALTCMPI = CxINC_RX       // Alternate Comparator Input bit (C1INC, C2INC and C3INC are on RB9)
#pragma config WDTCMX = WDTCLK          // WDT Clock Source Select bits (WDT clock source is determined by the WDTCLK Configuration bits)
#pragma config IESO = OFF               // Internal External Switchover (Disabled)

// CONFIG1
#pragma config WDTPS = PS32768          // Watchdog Timer Postscaler Select (1:32,768)
#pragma config FWPSA = PR128            // WDT Prescaler Ratio Select (1:128)
#pragma config WINDIS = OFF             // Windowed WDT Disable (Standard Watchdog Timer)
#pragma config FWDTEN = OFF             // Watchdog Timer Enable (WDT disabled in hardware; SWDTEN bit disabled)
#pragma config ICS = PGx1               // Emulator Pin Placement Select bits (Emulator functions are shared with PGEC1/PGED1)
#pragma config LPCFG = OFF              // Low power regulator control (Disabled - regardless of RETEN)
#pragma config GWRP = OFF               // General Segment Write Protect (Write to program memory allowed)
#pragma config GCP = OFF                // General Segment Code Protect (Code protection is disabled)
#pragma config JTAGEN = OFF             // JTAG Port Enable (Disabled)

#include
#include
#include


int main(void) {
    TRISBbits.TRISB15 = 1; //set LED port as input
    TRISBbits.TRISB11 = 1;
   
    ANSBbits.ANSB15 = 1; //set as analog
   
    //control register
    AD1CON1 = 0x2476;   //ADON adcon, discontinue if idle, PIA mode
    //Extended DMA & buffer off, 12 bit mode, decimal unsigned, internal counter
    // manual sample. sample and hold sampling
   
    AD1CON2 = 0;    //AVDD, ADSS reference voltages, sample &hold normal inputs
    //FIFO, no input scan, fill ADC1BUF0-7, interrupt every sample, fill start at ADC1BUf0, Always sample input select for A
   
    AD1CON3 = 0x1F02; //system clock, no extended sampling, disable charge pump,
    //31TAD sampling , 4 times TCY = TAD
   
    AD1CHS = 0x0009;
   
   
    ANCFG = 0;
    AD1CSSH = 0;
    AD1CSSL = 0;
    AD1CHITL = 0;
    ADC1BUF0 = -1;
    AD1CTMENL = 0;
    //IFS0bits.AD1IF = 0; // Clear A/D conversion interrupt.
   
    AD1CON1bits.ADON=1;
   
    int lightlevel[50];
   
    while(1)
    {   
        int i=0;
        while (i<50){
        //AD1CON1bits.SAMP = 1;
        __delay_ms(100);
        //AD1CON1bits.SAMP = 0;
        while (AD1CON1bits.DONE == 0){
            //lightlevel = ADC1BUF0;
            //AD1CON1bits.DONE = 0;
        }
        lightlevel = ADC1BUF0;
        //AD1CON1bits.DONE = 0;
        i++;
        }
    }
    return 1;
}

//  Example code for A/D ISR:
//void __attribute__ ((__interrupt__)) _ADC1Interrupt(void)
//{
//IFS0bits.AD1IF = 0;
//}

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