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大家好!我正面临着这个难题。我已经建立了一个跨阻抗放大器来放大光电二极管的信号,该光电二极管馈入PIC12F1822上的一个引脚,由ADC以1KHz进行采样,当采样发生时,这些采样通过串行与UART一起发送到PC。允许调谐增益的电路。由于无法使软件UART和I2C模块同时工作(尽管我确实使I2C自己工作),所以用I2C协议编程了数字的电阻值。然而,反馈电阻的NGE对其他人表现出奇怪的行为。如果我将数字罐编程为在大约125k-175k之间或在270k-370k之间,ADC提供的样品总是包括巨大的电压尖峰,但是如果我使用不同的电阻值,它们就不会出现。这种效果是100%可靠的,因为它们总是出现在这些范围中的值,而不会出现在外面的值。我在取样时用示波器观察放大器的输出,而示波器没有拾取电压尖峰,所以我相信它引入了一些伪影。ADC没有问题,因为我已经试过用固定的电阻值代替数字,同样的效果一直持续到如果我选择一个电阻值在可疑的范围内,如果我使用一个电阻值在它们之外就消失了。TWALE发出的话,它不会受到电阻值的影响。我也尝试过以不同的速率进行采样,但仍然会发生,所以我不认为这是某种混叠类型的影响(但又为什么它会依赖于阻力,如果是?)我还试着用同一种型号的芯片替换,以防我用的那个有毛病,仍然不走运。我在eevblog上看到一篇帖子,上面有个家伙在PWM的同时使用ADC,结果很奇怪。UART模块?我还是不相信这一点,为什么会对放大器中的电阻产生影响呢?我真的没有主意了。我已经上传了ADC正在接收的样本的图片,这里是示意图和示波器图片的链接。任何建议或想法,将不胜感激。
以上来自于百度翻译 以下为原文 Hello all! I am facing quite the puzzle. I have built a transimpedance amplifier to the amplify the signal of a photodiode which the feeds into a pin on a PIC12F1822 to be sampled by the ADC at 1KHz and these samples are then sent over serial with the UART to a PC, as the sampling is occuring. I have added a 1Mohm digipot to the amplifier circuit to allow for tuneable gain. The resistance value of the digipot is programmed with a I2C protocol which I have implemented with software bitbashing as I was unable to get the software UART and I2C modules to work concurrently (although I did get the I2C working by itself). The system works completely as expected for certain ranges of the feedback resistance, however exhibits strange behaviour for others. If I programme the digitpot to be between roughly 125k-175k or between 270k-370k the samples provided by the ADC always include huge voltage spikes, however if I use different resistance values, they do not appear. This effect is 100% reliable in that they always occur for values in these ranges and never occur for values outside. I am observing the output of the amplifier with an oscilloscope while sampling, and the oscilloscope is not picking up the voltage spikes, so I believe its some artifact introduced by the ADC. It's not a problem with the digipot itself, as I have tried replacing the digipot with a fixed resistor value and the same effects till persist if I choose a value of resistance within the dodgy ranges and disappears if I use one that has a value outside of them. I don't believe it's a software issue as then it wouldn't be effected by the resistance value. I have also tried sampling at a different rate and it still occurs, so I don't think it's some Aliasing type effect (but again why would it depend on resistance if it was?). I have also tried replacing the chip with another one of the same model, in case the one I was using was faulty and still no luck. I read a post on the eevblog where a guy was having weird ADC spikes from concurrently using the ADC at the same time as PWM, could my effect be due to concurrently using the UART module? I'm still not convinced by that as again, why would that effect on the resistance in the amplifier? I am truly out of ideas. I have uploaded a picture of the samples the ADC is receiving and (as you can only upload a single picture per post) here are links to the schematic and oscilloscope pictures. Any suggestions or ideas would be greatly appreciated. [ Attached Image(s) |
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13个回答
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放入100NF帽,没有改变任何东西。我还尝试了一个68K电阻,而不是在10K的一个(R5)的输入引脚,没有一个电阻器,没有运气。值得注意的是,当我把电阻器完全取出,把盖子连接到VSS(接地)上时,信号变得异常嘈杂,当我把盖子拿出来时,它又恢复正常了。我试着在照片DIO中添加了一个33 K,56K和150 K的电阻。DE和前两个也没有明显的区别,最后一个只是减弱了二极管的信号,但仍然有电压尖峰。我没有对第二个运算放大器做任何事情,这只是我已经拥有的包,这就是为什么我使用它。这是我用来设置的代码。模数转换器。我运行的时钟在16MHz,因此最快可能的ADC转换指定的纸张是我正在使用的(第132页的数据表)。ADCON1位。ADC=101;//设置FOS C/16 ADCONBITE。AdPREF=0;//设置VDD为VREF ADCONDOWS。CHS=0B00 01;//设置信道1作为从ADCON1BIT转换的AdFM=1;/ /右对齐ADCONDOWS。ADON=1;/ /开启ADC ON。
以上来自于百度翻译 以下为原文 Put in the 100nF cap, didn't change anything. I also tried with a 6.8K resistor instead on the 10k one (R5) on the input to the pin and without a resistor at all, no luck. Something which may be worth bringing to attention, when I took out the resistor completely and had the cap connecting the pin to Vss (ground) the signal became incredibly noisy, when I took the cap out, it went back to normal. I tried adding a 33k, 56k and 150k resistor in series with the photo diode and the first two also didn't make a noticeable difference and the last one just attenuated the signal from diode, but still had the voltage spikes. I'm not doing anything with the second op amp, that's just the package I already had which is why I used it. This is the code I'm using to set up the ADC. I am running the clock at 16MHz and so the fastest possible ADC conversion specified by the sheet is the one I'm using (page 132 of the data sheet). ADCON1bits.ADCS=101; //set FOS C/16 ADCON1bits.ADPREF=0; //set VDD as Vref ADCON0bits.CHS=0b0001; //set channel 1 as the one to convert from ADCON1bits.ADFM=1; //justify right ADCON0bits.ADON=1;// turn ADC on |
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你把它的输入连接到一个已知的状态了吗?如果没有,你可能已经建立了一个自由运行的振荡器。
以上来自于百度翻译 以下为原文 Have you tied its inputs to a known state? If not, you may have built a free running oscillator. |
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我不会排除这个软件的。看起来非常像整数溢出或类似的东西。
以上来自于百度翻译 以下为原文 I wouldn't rule out the software. Looks very much like integer overflows or something of that sort. |
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您是否在项目中测试多个ADC通道?
以上来自于百度翻译 以下为原文 Are you testing multiple ADC channels in your project per chance? |
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我能找到TB3142的技术简报来描述干扰的原因。我在本文中列出了一段背景引文供您参考。引号数字逻辑用于控制模拟信道多路复用器(MUX)。作为使用数字逻辑在模拟(ADC)通道之间切换的一个伪影,来自不同设备引脚的信号可以瞬间连接。当ADC输入通道被切换时,两个不相关的I/O引脚可以连接。I/O可以连接信号通过MUX向上传播以触发ADC信道改变的时间。
以上来自于百度翻译 以下为原文 I was able to find the tech brief TB3142 that might describe the cause of the disturbance. I listed a quote from the background paragraph in the document for your reference. Quote Digital logic is utilized in controlling the analog channel multiplexer (MUX). As an artifact of using digital logic to switch between analog (ADC) channels, signals from different device pins can momentarily be connected. Two unrelated I/O pins can become connected when the ADC input channels are switched. The I/O can connect for the amount of time it takes the signal to propagate through the MUX to trigger the ADC channel to change. Unquote |
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可能你违反了最大的ADC时钟速率规格?您没有指定您的FoSC,但在FoC/16的ADC时钟上,数据表说明Fosc应该在4到16 MHz之间。改变到FoSC/32给出8到32 MHz可接受的Fosc。
以上来自于百度翻译 以下为原文 Possibly you were violating the maximum ADC clock rate spec? You did not specify your Fosc but at an ADC clock of Fosc/16 the data sheet states that Fosc should be between 4 and 16 Mhz.(table 16-1). Changing to Fosc/32 gives 8 to 32 Mhz acceptable Fosc. |
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是的,错过了。这样就可以用Fosc / 16把它放在边缘。也许Fosc / 32工作的原因。TAD被指定为1 USEC最小值,所以如果时钟有点快……
以上来自于百度翻译 以下为原文 Yep, missed that. So that puts it right on the edge with Fosc/16. Possibly why Fosc/32 works OK. Tad is specified as 1 usec minimum so if the clock is a little fast...... |
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为了发展我的理解,有人知道我的电路为什么会造成ADC的行为方式,以及为什么放慢速度会修复它?我应该在这个帖子真的很新鲜的时候问这个问题,但是我已经松了一口气。
以上来自于百度翻译 以下为原文 For the sake of developing my understanding, does anyone know why my circuit would be causing the ADC behave in the way it was and why slowing it down would fix it? I should've asked this at the time this post was still fresh really, but I was just relieved to have gotten it working. |
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你是否允许足够的采集时间?这一点被记录在“A/D获取要求”章节中。减慢时钟可能会放松需求。
以上来自于百度翻译 以下为原文 Were you allowing sufficient acquisition time? This is documented in the chapter "A/D Acquisition Requirements". Slowing the clock may relaxed the requirements a bit. |
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“获取”发生在GO/DONE位清晰的时候。如果您的定时器只是将位设置为1kHz,并且转换花费远远小于1ms,那么您肯定会有大量的获取时间。
以上来自于百度翻译 以下为原文 "Acquisition" occurs while the GO/DONE bit is clear. If your timer was only setting the bit at 1kHz, and the conversion was taking much less than 1ms, then you would certainly have plenty of acquisition time. |
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更令人困惑的是,运算放大器反馈电阻影响了转换精度。它与转化率之间没有交互作用。
以上来自于百度翻译 以下为原文 What is even more puzzling is that the opamp feedback resistor was influencing the conversion accuracy. There should be no interaction between it and the conversion rate. |
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