n00b关于以太网的内核与VHDL的问题

建议你，xilinx_temp_9099  -
这个帖子接近40个帖子，也许只有3个帖子是一般论坛人群的有趣话题。
为什么不开始一个新的线程，在那里可以讨论你的设计的技术方面而没有所有非技术性的“干扰”。
我们可以保留这个帖子，包含非技术性戏剧和狡猾机智表达的新帖子，所以你的新帖子不会再被稀释。
这有意义吗？
圣诞节快乐 ！！
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
您的代码中的评论不需要支付额外费用。
我没有支付论坛帖子的费用。
如果我写一篇好文章，那么我一无所获。



以下为原文

Suggestion for you, xilinx_temp_9099 --
 
This thread is close to 40 posts long, and maybe only 3 of them are interesting topical issues for the general forum population.
 
Why not start a new thread, where your design's technical aspects can be discussed without all the non-technical "distractions".  We can keep this thread around for new postings containing non-technical drama and expressions of snarky wit, so your new thread won't be diluted again.
 
Does this make sense?
 
Merry Christmas !!
 
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

是的，我看到的“bug”出现在我的代码中。
我错误地看到xilinx“已知问题”具有相同的错误消息，但它是用于实例化特定的verilog模块IOBUFDS。
“这会让你......半光泽，半滑溜溜？
一个闪亮的漫步？
dtroll？
对于demi-droll而言是那个公制欧元峰值，就像半滑车一样？
什么是demi-droll的另一半，ashton-droll？
（曾经是布鲁斯 - 戴尔）？
- 鲍勃“随机”Elkind
“
你是对的鲍勃，我应该坚持主题。



以下为原文

yes, the "bug" I saw was in my code. I incorrectly saw a xilinx "known issue" with the same error message, but it was for instantiating a specific verilog module IOBUFDS.
 
 
" And that makes you...  half shiny and half droll?

A shiny dtroll?

dtroll?  is that metric eurospeak for demi-droll, as in half-droll?
 
What is the other half of a demi-droll, an ashton-droll?    (used to be a bruce-droll) ?
 
-- Bob "random" Elkind
"
 
You're right Bob, I should stick to the subject matter.

你是对的鲍勃，我应该坚持主题。
这是你的电话，只是一个建议：打开一个新的 - 清晰的线程。
在这个主题中继续论坛评论可能是一个好主意，并在一个单独的线程中讨论技术问题。
有一个好的假期。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
您的代码中的评论不需要支付额外费用。
我没有支付论坛帖子的费用。
如果我写一篇好文章，那么我一无所获。



以下为原文

You're right Bob, I should stick to the subject matter.

It's your call, just a suggestion:  to open a new - and clear - thread.
It may be a good idea to continue with forum commentary in this thread, and discuss technical issues in a separate thread.
 
Have a good holiday.
 
- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

好吧，有一件好事正在发生 - 我昨晚为linux下载了ISE 12并完全正常工作。
下载电缆有很多麻烦，但我希望用Linux这样的东西。
我用过这个开源驱动程序：
http://rmdir.de/~michael/xilinx/
readme.txt非常有助于它在我的架构上运行（amd 64 bit gentoo linux kernel 2.6.31）。
如果任何人有任何问题让他们的ISE使用此配置让我知道。
我必须操作udev并安装虚拟并行端口驱动程序。
但总的来说它看起来很不错，这是我在2006年第一次使用ISE / Linux版本8时的巨大改进。再加上能够直接在linux中编辑和实现我的设计，对我来说速度极快。
更多即将到来。
圣诞节快乐。



以下为原文

well one good thing is happening - I downloaded ISE 12 last night for linux and have it completely working. Had a lot of trouble with the download cable but I expect things like that with Linux.
 
I used this open source driver:
 
http://rmdir.de/~michael/xilinx/
 
the readme.txt was very helpful in getting it working on my architecture (amd 64 bit gentoo linux kernel 2.6.31 ). If anyone has any problems getting their ISE to work with this configuration let me know. I had to maneuvre udev and install dummy parallel port drivers. but overall it looks good and is a tremendous improvement from my first go-around with ISE/Linux ver 8 back in 2006. Plus being able to edit and implement my designs directly in linux will speed things up tremendously for me. More to come soon.
 
merry christmas.

周末我取得了一些进展。
我附上了一个例子，它简单地从PHY上复制5个RXD引脚并相应地点亮LED组。
我在linux上使用多播C ++程序测试它，并确认当我发送多播帧时灯会亮起，当我停止程序时它们会关闭。
这是一个好的开始。
当然没有IP地址，没有TCP或网络层。
这只是简单的UDP，不会对数据包执行任何操作。
但是有比立即可见的更多的进展：我从在线附加另一个示例应用程序，将“FPGA”写入LCD屏幕。
我学会了如何实例化组件，以便PHY等模块可以存在于自己的文件中。
这将在以后发挥重要作用，以便在尝试TCP / IP时，该项目不会在其自身的复杂性下崩溃。
最难的部分将是DDR SDRAM，再次，弄清楚如何使用组件是很大的。
现在我坚持使用VHDL，尽管我听说verilog对于程序设计更好。
要使用这些文件，只需将它们添加到空白ISE项目中即可。
这适用于ISE 12.如果您遇到重大问题请告诉我，我将上传整个项目目录。
我的下一个阶段是尝试解析udp数据包并将一些文本打印到LCD上。
这将需要LCD的通用接口来解析和打印字符串，因此这些组件实例化将真正帮助我。
更多即将到来。
phy0.tgz 3 KB



以下为原文

I made some more progress over the weekend. I have attached an example that simply copies 5 RXD pins off the PHY and lights up the LED bank accordingly. I tested it with a multicast C++ program on linux and confirmed that the lights come on when I send multicast frames and they shut off when I stop the program. This is a good start.
 
There is of course no IP address, no TCP or network layer. This is just simple UDP that doesn't do anything with the packets. But there is more progress than what is immediately visible: I attached another example app from online that writes "FPGA" to the LCD screen. I learned how to instantiate components so that modules such as the PHY can live in their own file. This will be critical later on so that this project doesn't implode under its own complexity , if and when TCP/IP is attempted.  The hardest part later on will be incorporating the DDR SDRAM, and again, figuring out how to use components is big.
 
For now I'm sticking with VHDL, even though I hear verilog is better for procedural designs. To use these files, simply add them to a blank ISE project. This works great with ISE 12. If you are having major trouble let me know and I'll upload the whole project directory.
 
My next phase is going to be to try parsing udp packets and printing some of the text to the LCD. This will require a generic interface to the LCD to just parse and print a string, so these component instantiations will really help me out. More to come soon.
 
 
            phy0.tgz ‏3 KB

一些建议：您在设计中使用了异步重置。
使用FPGA时，除非绝对必要，否则应避免异步复位。
有关更多信息，请参阅Xilinx WP272获取智能关于重置：思考本地，而不是全局。
如果可能，请完全避免重置：通常可以将重置限制为控制逻辑并保持数据路径不重置。
阿德里安
请在询问之前先查询您的问题。如果有人回答您的问题，请在“接受为解决方案”标记该帖子。
如果你看到一个特别好的和信息丰富的帖子，考虑给它Kudos（左边的星）。



以下为原文

Some advice: you used asynchronous resets in your design. When working with FPGAs, you should avoid asynchronous resets except if absolutely necessary. For more information, see Xilinx WP272 Get Smart About Reset: Think Local, Not Global.
If possible, avoid resets alltogether: often it is possible to restrict the reset to control logic and leave the data path without resets.
 
 
Adrian

Please google your question before asking it.
If someone answers your question, mark the post with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left).

awillen  - 非常感谢您的设计提示。
这是一种微妙的错误，肯定会让有经验的设计师知道。
与代码中显而易见的东西相比，我可以通过反复试验来修复。
我肯定会在某些时候将它融入我的设计中。
我将进入这个设计的下一个阶段，即使用DDR SDRAM作为phy的缓冲区。
我要感谢Mike Johnson和他在这里的spartan-3e上的VHDL开源pacman程序
http://www.fpgaarcade.com/pac_main.htm
这对于查看更大规模的设计示例以及如何合并不同组件非常有帮助。
当然pacman本身不支持以太网:)但他的代码非常有用。
不幸的是，我没有使用vga电缆来看看pacman游戏是否实际播放，但我敢打赌。
接下来我将尝试使LCD从显示“FPGA”变为实际从DDR读取32个字节并显示它。
也许在那之后我会尝试启用旋钮，这样你就可以向下滚动内存。
如果我可以让它工作，下一阶段将使PHY写入内存，实质上是将UDP帧转储到LCD。
我会用我发现的东西报告。
也许pacman作者有一天可以使用我的以太网代码并将其重新整合到他的设计中，以允许您通过UDP连接与世界各地的人们玩pacman：P



以下为原文

awillen - thank you very much for the design tip. That's the type of subtle bug that would definitely take an experienced designer to know about. versus something obvious in code that I could fix by trial and error. I will definitely incorporate that into my design at some point.
 
I am going to move to the next phase of this design, which will be to use the DDR SDRAM as a buffer off the phy. I want to thank Mike Johnson and his open source pacman program for VHDL on the spartan-3e which he has here
 
http://www.fpgaarcade.com/pac_main.htm
 
This was a great help in seeing a larger-scale design example and how to incorporate different components. of course pacman itself isn't ethernet enabled :) but his code was extremely useful. Unfortunately I didn't have a vga cable to see if the pacman game actually played but I bet it does.
 
Next I will attempt to make the LCD go from just displaying "FPGA" to actually reading 32 bytes from DDR and displaying it. Perhaps after that I will try enabling the rotary knob so you can scroll down the memory.
 
If I can get that to work, the next phase will be getting the PHY to write to memory, essentially dumping the UDP frame to the LCD. I will report back with what i find. Perhaps the pacman author can someday use my ethernet code and incorporate it back into his design to allow you to play pacman against people worldwide via a UDP connection :P
 
 

嘿伙计们，我只想发布更新。
我将离开这个项目至少一周或两周，所以我想我会发布我所取得的进展：
*我启用了DDR ram。此时，DDR实际上并没有存储PHY数据，但我确认写操作在phy.vhd模块中，当你手动写“0x30”/“0x31”时，你
将在液晶显示屏上看到“0”或“1”。
PHY不能工作的原因是由于时钟/定时，字符不可读，或者可能是它们被解码的逻辑错误。
我相信我可以自己解决这个问题。
*我启用了LCD并解码了大部分有用的字符。
它目前显示'？'
对于不在范围内的字符，因为我没有使用地图上的japanese / I-dunno字符。
目前，代码写入LCD的下一行，因为我正在调整地址字节。
最后，我希望旋钮控制FPGA正在读取的RAM的地址，并在顶行显示数据，地址在底行，或者只是将数据转储到两行。
*我启用了旋钮。
这个想法是这样的：旋钮产生一个由LCD读入的输出信号。
然后LCD从RAM读取该地址并显示（如果可以）面板上的字节。
这样，我可以从计算机上写一个“hello world”多播UDP数据包，然后滚动浏览所有数据包标题和其他垃圾，直到我到达有效负载，并最终在液晶屏上看到“Hello world”，当我
终于到了有效载荷。
PHY只有一个本地地址，它会随着它解码的每个字节递增 - 它不关心旋钮在做什么。
目前，旋钮将信号发送到LCD模块，但有一个错误，我不确定LCD是否正在读取地址，因此LCD模块只是在您旋转旋钮时点亮LED。
现在我知道LCD正在接收信号，我可以继续调试DDR ram。
*我使用多路复用器（希望）控制对ram的访问。
PHY是生产者，LCD是消费者。
通过使用HOLD /“ram busy”行可能有一种方法可以在没有多路复用器的情况下执行此操作，但我得到了可怕的“多个驱动程序的信号”错误。
我不知道。
下一步是真正了解LCD清晰序列。
起初我只是天真地试图重新设置整个LCD，每次我想要它，但显然这是糟糕的设计。
我只需要学习如何编写清除字节并使其移动。
然后我需要让ram滚动功能工作。
我可能需要一个去抖动旋钮，但主要是我想将串行数据写入DDR，如“12345”，当我转动旋钮时，看到它滚动到LCD。
然后，我将专注于正确解码PHY数据。
我正在学习这项工作，希望有一天这个项目对人们有用。
如果你想查看代码，我肯定会接受任何有关它的建议，但是现在我只是张贴以显示我正在进行的进展。
一旦我可以收到帧，我将努力发送它们。
然后我将介绍TCP / IP。
如果一切都保持模块化，TCP / IP可能最终只是一系列状态机，其信号触发预定义的数据包。
但我还有很长的路要走。
PHY.tgz 11 KB



以下为原文

hey guys, I just wanted to post an update. I am going to be away from this project for at least a week or 2, so I thought I'd post the progress I've made:
 
* I enabled the DDR ram.At this point, the DDR doesn't actually store PHY data yet, however i confirmed that the write works in the phy.vhd module, and when you write "0x30" / "0x31" manually, you will see '0' or '1' on the lcd. The reason the PHY doesn't work yet is either due to clocking / timing, the characters not being readable, or possibly a logical bug in the way they're being decoded. I am sure I can fix this on my own.
 
* I enabled the LCD and decoded most of the useful characters for it. it currently displays '?' for characters not in the range, since I have no use for the japanese/I-dunno characters on the map. Currently the code writes to the lower row of the LCD since i was tweaking with the address byte. Ultimately I want the rotary knob to control the address of RAM from which the FPGA is reading, and either display the data in the top row with the address in the bottom row, or just dump data to both rows.
 
* I enabled the rotary knob. The idea is this: the knob generates an output signal that is read in by the LCD. The LCD then reads this address from RAM and displays (if it can ) the byte on the panel. This way, I can write a "hello world" multicast UDP packet from the computer, and then scroll past all the packet headers and other junk until I get to the payload, and eventually see "Hello world" on the LCD screen, when I finally get to the payload. The PHY just has a local address that keeps incrementing with every byte that it decodes - it doesn't care what the knob is doing. Currently, the knob sends the signal to the LCD module, but there was a bug and I wasn't sure if the LCD was reading the address, so the LCD module just lights up the LEDS as you turn the knob. Now that I know the LCD is receiving the signal properly, I can resume debugging the DDR ram.
 
* I used a multiplexer to (hopefully) control access to the ram. The PHY is the producer and the LCD is the consumer. There may be a way to do this without a mux by using the HOLD / "ram busy" line, but I was getting the dreaded "multiple drivers for a signal" error. I don't know.
 
The next step is to really understand the LCD clear sequence. At first I just naively tried resetting the whole LCD every time I wanted to referesh it, but obviously that's poor design. i just have to learn how to write the clear byte and get it moving. 
 
Then I need to get the ram scrolling feature to work. I may need a debouncer for the knob, but mostly i want to write serial data to the DDR like "12345" and see it scroll through teh LCD as I turn the knob. Then, I will focus on getting the PHY data decoded properly.
 
 
I'm learning a ton doing this and hopefully this project will be useful to people someday. I will definitely take anyones advice about it if you want to look at the code, but for now I'm just posting to show the progress I'm making. Once I can receive frames, I will work on sending them. Then I will look in to TCP/IP. If everything stays modular, TCP/IP may end up just being a series of state machines with signals that trigger predefined packets. But I've got a long way to go.
            PHY.tgz ‏11 KB